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authoriximeow <me@iximeow.net>2025-10-19 23:06:14 +0000
committeriximeow <me@iximeow.net>2025-10-19 23:29:05 +0000
commit06949d312514850645f3c2bcaa3e0cdc95a6c545 (patch)
tree01ab7a04881ec4d00bb8ec2cd6a7ff3e8b7660f3 /src/armv7.rs
parentfd00bf73f7722654473e8fdafa704852df176d2c (diff)
Opcode and Operand should be non-exhaustive
but exhaustiveness checking is very valuable here, so allow it to be disabled. caveats apply. read the docs in Cargo.toml.
Diffstat (limited to 'src/armv7.rs')
-rw-r--r--src/armv7.rs2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/armv7.rs b/src/armv7.rs
index b1ae2ba..3e289b6 100644
--- a/src/armv7.rs
+++ b/src/armv7.rs
@@ -39,6 +39,7 @@ pub struct NoContext;
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[allow(non_camel_case_types)]
#[allow(missing_docs)]
+#[cfg_attr(feature = "non-exhaustive-enums", non_exhaustive)]
pub enum Opcode {
Invalid,
/*
@@ -606,6 +607,7 @@ impl StatusRegMask {
/// an operand in an `arm` instruction.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "non-exhaustive-enums", non_exhaustive)]
pub enum Operand {
/// a general-purpose register.
Reg(Reg),