diff options
| author | iximeow <me@iximeow.net> | 2026-09-11 15:57:22 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-09-11 16:18:53 +0000 |
| commit | a00a54539d9124d8b376ee9cbeab355d99c9d163 (patch) | |
| tree | 85ee14db687c5590c2bbea8eed1589f4088f969c /src/armv7.rs | |
| parent | 7e70f851a481d36669e64edcd61ce7df9d578468 (diff) | |
fix {s,u}xt{h,b}[16] using an immediate to describe their rotates
Diffstat (limited to 'src/armv7.rs')
| -rw-r--r-- | src/armv7.rs | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/armv7.rs b/src/armv7.rs index 87b44f5..30a8960 100644 --- a/src/armv7.rs +++ b/src/armv7.rs @@ -775,6 +775,10 @@ pub enum Operand { BankedSPSR(Bank), /// a mask of bits for the `spsr` register. StatusRegMask(StatusRegMask), + /// a standalone rotate right by the specified amount. + /// + /// this typically applies equally to multiple operands; see `sxtah`, `uxtah`, etc. + Ror(u8), /// the `apsr` register. APSR, /// the `spsr` register. @@ -846,6 +850,8 @@ pub trait OperandVisitor { fn visit_banked_spsr(&mut self, bank: Bank) -> Result<Self::Ok, Self::Error>; /// process an operand that is some set of bits out of a status register. fn visit_status_reg_mask(&mut self, mask: StatusRegMask) -> Result<Self::Ok, Self::Error>; + /// process an operand that is a standalone rotate of other operands in the instruction. + fn visit_rotate(&mut self, amt: u8) -> Result<Self::Ok, Self::Error>; /// process an operand that is `APSR`. fn visit_apsr(&mut self) -> Result<Self::Ok, Self::Error>; /// process an operand that is `SPSR`. |
