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| author | Brandon Ros <brandonros1@gmail.com> | 2026-07-03 20:48:35 -0400 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-07-28 02:53:24 +0000 |
| commit | bbbb546ee0b73d295be891b1b2e0e5a18cbfd3d1 (patch) | |
| tree | 7f20df891883d5d60a7a366d16e76b286ac91b64 /src/armv7.rs | |
| parent | 9e9c7b2663fa52881bf6883e74f4cd8610c38570 (diff) | |
fix thumb2 TBH decode: wrong opcode and register-shift operand
the T1 TBH arm set Opcode::TBB instead of Opcode::TBH, and built the
index operand with bit 4 set in the RegShift raw value. bit 4 is the
RegReg selector in RegShift::into_shift, so the mandatory 'lsl #1' index
scaling decoded as a register shift 'lsl r0' instead. clear bit 4 so it
reads back as the RegImm 'lsl #1' the encoding specifies.
verified against binutils objdump: df e8 13 f0 is tbh [pc, r3, lsl #1].
Diffstat (limited to 'src/armv7.rs')
0 files changed, 0 insertions, 0 deletions