diff options
| author | iximeow <me@iximeow.net> | 2026-07-26 00:34:41 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-07-28 02:53:24 +0000 |
| commit | e987f1c7ea59ed2e7d09368e7b110fc213f00ff9 (patch) | |
| tree | cce124e30362612a70c79fef1df9d4b29c5b4e2d /src/armv7.rs | |
| parent | cb36e55f64ae1a941b20d2d6d6b5e546566072f8 (diff) | |
probably should decide where imm-shifted reg normalization happens
Diffstat (limited to 'src/armv7.rs')
| -rw-r--r-- | src/armv7.rs | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/armv7.rs b/src/armv7.rs index 2403eaa..0b43ed8 100644 --- a/src/armv7.rs +++ b/src/armv7.rs @@ -2559,15 +2559,21 @@ impl Decoder<ARMv7> for InstDecoder { }; let last_operand = if shift_spec & 0xff0 == 0 { - // No shift, so the operand is just a register + // no shift, so the operand is just a register. + // + // TODO: this shift style is `lsl 0`, and not incorrect to report + // as just that. should it be impossible for `format_reg_shift` to + // get a register shifted by lsl 0? simplifying the register here + // seems valuable for consumers of individual operands. as-is, this + // is inconsistent across the library, which is probably the worst + // it could be... Operand::Reg(Reg::from_u8(Rm)) } else { Operand::RegShift(RegShift::from_raw(shift_spec)) }; match inst.opcode { - Opcode::MOV - |Opcode::MVN => { + Opcode::MOV | Opcode::MVN => { if self.should_is_must { if Rn != 0 { return Err(DecodeError::Nonconforming); @@ -2581,8 +2587,7 @@ impl Decoder<ARMv7> for InstDecoder { ]; } - Opcode::CMP - |Opcode::CMN => { + Opcode::CMP | Opcode::CMN => { if self.should_is_must { if Rd != 0 { return Err(DecodeError::Nonconforming); |