Test Target, fix bogus MRS destinations

2 files changed, 33 insertions, 0 deletions

diff --git a/src/armv7/display.rs b/src/armv7/display.rs
index 6673fcd..91affeb 100644
--- a/src/armv7/display.rs
+++ b/src/armv7/display.rs
@@ -964,6 +964,7 @@ impl <T: fmt::Write, Y: YaxColors> Colorize<T, Y> for ConditionedOpcode {
             Opcode::DSB |
             Opcode::CSDB |
             Opcode::SRS(_, _) |
+            Opcode::TT { .. } |
             Opcode::BKPT => { write!(out, "{}", colors.misc_op(self)) },
 
             Opcode::DBG |
@@ -1262,6 +1263,11 @@ impl Opcode {
             Opcode::USUB8 => { "usub8" },
             Opcode::UQSUB8 => { "uqsub8" },
             Opcode::UHSUB8 => { "uhsub8" },
+
+            Opcode::TT { alternate: false, unprivileged: false } => "tt",
+            Opcode::TT { alternate: true, unprivileged: false } => "tta",
+            Opcode::TT { alternate: false, unprivileged: true } => "ttt",
+            Opcode::TT { alternate: true, unprivileged: true } => "ttat",
         }
     }
 }
diff --git a/src/armv7/thumb.rs b/src/armv7/thumb.rs
index 16d671a..72a2ea6 100644
--- a/src/armv7/thumb.rs
+++ b/src/armv7/thumb.rs
@@ -147,6 +147,33 @@ pub fn decode_into<T: Reader<<ARMv7 as Arch>::Address, <ARMv7 as Arch>::Word>>(d
                         match op1op2 {
                             0b0000 => {
                                 // `STREX` (`A8-691`)
+                                // v8.something
+
+                                // TODO: isa version flags
+                                if rt == 15 /* && decoder.armv8 */ {
+                                    if imm8 & 0b0011_1111 != 0 {
+                                        if decoder.should_is_must {
+                                            return Err(DecodeError::Nonconforming);
+                                        }
+                                    }
+                                    let at = imm8 >> 6;
+                                    inst.opcode = Opcode::TT {
+                                        alternate: (at >> 1) != 0,
+                                        unprivileged: (at & 1) != 0,
+                                    };
+                                    if rd == 13 || rd == 15 || rn == 15 {
+                                        decoder.unpredictable()?;
+                                    }
+                                    inst.operands = [
+                                        Operand::Reg(Reg::from_u8(rd)),
+                                        Operand::Reg(Reg::from_u8(rn)),
+                                        Operand::Nothing,
+                                        Operand::Nothing,
+                                    ];
+
+                                    return Ok(());
+                                }
+
                                 // v6T2
                                 if rd == 13 || rd == 15 || rt == 13 || rt == 15 || rn == 15 {
                                     decoder.unpredictable()?;