diff options
| author | iximeow <me@iximeow.net> | 2024-03-17 08:56:24 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2024-03-17 08:56:24 +0000 |
| commit | c3f1cd87d7d504841e0221309c53f4d009bf2b22 (patch) | |
| tree | 35805f544177a85bd588890ae2a4d65a1c6397fe /src | |
| parent | 85456e92b038f6e7c75c8714fb8dd4331e813c79 (diff) | |
fix uxtb/uxth alias being incorrectly applied with x-size registers
Diffstat (limited to 'src')
| -rw-r--r-- | src/armv8/a64.rs | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/src/armv8/a64.rs b/src/armv8/a64.rs index c697c76..4cd91da 100644 --- a/src/armv8/a64.rs +++ b/src/armv8/a64.rs @@ -444,21 +444,15 @@ impl Display for Instruction { }, Opcode::UBFM => { // TODO: handle ubfx alias - if let Operand::Immediate(0) = self.operands[2] { - let newdest = if let Operand::Register(_size, destnum) = self.operands[0] { - Operand::Register(SizeCode::W, destnum) - } else { - unreachable!("operand 1 is always a register"); - }; - let newsrc = if let Operand::Register(_size, srcnum) = self.operands[1] { - Operand::Register(SizeCode::W, srcnum) - } else { - unreachable!("operand 1 is always a register"); - }; + if let ( + Operand::Register(SizeCode::W, destnum), + Operand::Register(SizeCode::W, srcnum), + Operand::Immediate(0) + ) = (self.operands[0], self.operands[1], self.operands[2]) { if let Operand::Immediate(7) = self.operands[3] { - return write!(fmt, "uxtb {}, {}", newdest, newsrc); + return write!(fmt, "uxtb {}, {}", self.operands[0], self.operands[1]); } else if let Operand::Immediate(15) = self.operands[3] { - return write!(fmt, "uxth {}, {}", newdest, newsrc); + return write!(fmt, "uxth {}, {}", self.operands[0], self.operands[1]); } } if let Operand::Immediate(imms) = self.operands[3] { |