diff options
| -rw-r--r-- | CHANGELOG | 1 | ||||
| -rw-r--r-- | src/armv7/thumb.rs | 6 | ||||
| -rw-r--r-- | tests/armv7/thumb.rs | 28 |
3 files changed, 32 insertions, 3 deletions
@@ -16,6 +16,7 @@ saved) program status register, was reported as a banked GPR. * thumb2: some coprocessor instructions were incorrectly decoded as `ldc*/stc*` * thumb2: fix missing decode of `s` bit for wide lsl/lsr/asr/ror (register) +* thumb2: rfeia and rfedb were decoded backwards. likewise for srsia and srsdb * ARMv8: support thumb2 encoding of `Test Target` instruction, `Opcode::TT` (formatted as any of `tt`, `ttt`, `tta`, `ttat`) * ARMv8: formerly-coprocessor instructions have been defined into SIMD extensions, diff --git a/src/armv7/thumb.rs b/src/armv7/thumb.rs index 18b4526..ab3f94b 100644 --- a/src/armv7/thumb.rs +++ b/src/armv7/thumb.rs @@ -613,7 +613,7 @@ pub fn decode_into<T: Reader<<ARMv7 as Arch>::Address, <ARMv7 as Arch>::Word>>(d 0b00 => { // `SRS (Thumb)` (`B9-1990`) // v6T2 - inst.opcode = Opcode::SRS(false, true); // `srsdb` + inst.opcode = Opcode::SRS(true, false); // `srsdb` inst.operands = [ Operand::RegWBack(Reg::from_u8(13), w), Operand::Imm12(lower2[0..4].load::<u16>()), // #<mode> ? what's the syntax here? #<the literal>? @@ -710,7 +710,7 @@ pub fn decode_into<T: Reader<<ARMv7 as Arch>::Address, <ARMv7 as Arch>::Word>>(d if rn == 15 { decoder.unpredictable()?; } - inst.opcode = Opcode::RFE(false, true); + inst.opcode = Opcode::RFE(true, false); inst.operands = [ Operand::RegWBack(Reg::from_u8(rn), w), Operand::Nothing, @@ -775,7 +775,7 @@ pub fn decode_into<T: Reader<<ARMv7 as Arch>::Address, <ARMv7 as Arch>::Word>>(d if rn == 15 { decoder.unpredictable()?; } - inst.opcode = Opcode::RFE(true, false); + inst.opcode = Opcode::RFE(false, true); inst.operands = [ Operand::RegWBack(Reg::from_u8(rn), w), Operand::Nothing, diff --git a/tests/armv7/thumb.rs b/tests/armv7/thumb.rs index defdacb..b7b43d3 100644 --- a/tests/armv7/thumb.rs +++ b/tests/armv7/thumb.rs @@ -4684,6 +4684,34 @@ fn test_target() { } #[test] +fn test_rfe_srs() { + test_display( + &[0xb0, 0xe9, 0x00, 0xc0], + "rfeia.w r0!" + ); + test_display( + &[0x30, 0xe8, 0x00, 0xc0], + "rfedb.w r0!" + ); + test_display( + &[0x0d, 0xe8, 0x09, 0xc0], + "srsdb.w sp, 0x9" + ); + test_display( + &[0x8d, 0xe9, 0x09, 0xc0], + "srsia.w sp, 0x9" + ); + test_display( + &[0x2d, 0xe8, 0x09, 0xc0], + "srsdb.w sp!, 0x9" + ); + test_display( + &[0xad, 0xe9, 0x09, 0xc0], + "srsia.w sp!, 0x9" + ); +} + +#[test] fn test_decode_tbh_operand_shape() { use yaxpeax_arm::armv7::{Opcode, Operand, RegShiftStyle, ShiftStyle}; |