| Age | Commit message (Expand) | Author |
|---|
| 6 hours | fix hvc immediate missing its upper four bits | iximeow |
| 6 hours | fix ssat/16 second operand off by one, testcases | iximeow |
| 6 hours | fix issues around unpredictable ldrd and offset printing | iximeow |
| 6 hours | fix {s,u}xt{h,b}[16] using an immediate to describe their rotates | iximeow |
| 6 hours | fix mrc/mrc2 use of CRd=15 | iximeow |
| 6 hours | thumb differential test must handle shift descriptions, other refinements | iximeow |
| 6 hours | more lining up differential tests | iximeow |
| 2026-08-06 | cdp/mrc/mcr opc1 is wider than display knows | iximeow |
| 2026-08-04 | write condition code *before* .w suffix | iximeow |
| 2026-08-04 | more leftover capstone cs_insn reuse stuff | iximeow |
| 2026-08-04 | msr confusion like with mrs.. | iximeow |
| 2026-08-03 | use cs_disasm() to stop inheriting bogus cc state | iximeow |
| 2026-08-03 | armv8 thumb-mode hints | iximeow |
| 2026-08-03 | wip differential support (differences mostly understood) | iximeow |
| 2026-08-03 | decode unknown wide hints like any other hints | iximeow |
| 2026-08-03 | thumb differential: much more reasonable operand parsing for memory ops.. | iximeow |
| 2026-08-02 | fix swapped rfe{ia,db} and srs{ia,db} | iximeow |
| 2026-08-02 | fix missing decode of `s` bit for wide shift/rotate ops | iximeow |
| 2026-08-02 | thumb ldc/stc encodings missed a bit | iximeow |
| 2026-08-02 | sufficiently advanced SIMD is indistinguishable from coprocessors | iximeow |
| 2026-08-02 | thumb2 preload improvements | iximeow |
| 2026-08-02 | thumb SIMD encoding should have returned Incomplete | iximeow |
| 2026-08-02 | pkhbt/pkhtb bitmask confusion | iximeow |
| 2026-08-02 | Test Target, fix bogus MRS destinations | iximeow |
| 2026-08-02 | ldrexd changelog | iximeow |
| 2026-08-02 | thumb mrs/msr first operand was wildly wrong | iximeow |
| 2026-07-28 | temp, armv8-thumb | iximeow |
| 2026-07-28 | thumb2: fix parallel addition/subtraction, (un)signed | iximeow |
| 2026-07-28 | thumb: when nonconforming, allow it/cond=1111 like capstone | iximeow |
| 2026-07-28 | thumb differential: segment out a few categories of diff | iximeow |
| 2026-07-28 | capstone prints thumb add/sub sp+immediate as two operands | iximeow |
| 2026-07-28 | differential test should tolerate a few more differences | iximeow |
| 2026-07-28 | untangle some nonconforming ld/st forms | iximeow |
| 2026-07-28 | lsl/mov aliasing | iximeow |
| 2026-07-28 | differential testing wip | iximeow |
| 2026-07-28 | fix thumb2 TBH decode: wrong opcode and register-shift operand | Brandon Ros |
| 2026-07-28 | fix more thumb2 register data-processing decode bugs | Brandon Ros |
| 2026-07-28 | some armv7/thumb arms are basically duplicate | iximeow |
| 2026-07-28 | fix several thumb2 decode bugs | Brandon Ros |
| 2026-07-28 | Do not add an 's' when outputing opcodes that always set flags | Grond |
| 2026-07-28 | Decode the correct number of operands for TST/TEQ (immediate/register) | Grond |
| 2026-07-28 | Simplify decoding of register-shifted-register data-processing instructions | Grond |
| 2026-07-28 | probably should decide where imm-shifted reg normalization happens | iximeow |
| 2026-07-28 | Decode the correct number of operands for CMP/CMN (immediate/register) | Grond |
| 2026-07-28 | Fix the handling of reserved bits in uncommon loads/stores | Grond |
| 2026-07-28 | Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2 | Grond |
| 2026-07-28 | Implement the RRX immediate shift type | Grond |
| 2026-07-28 | Fix the handling of arithmetic register shifts with zero immediates | Grond |
| 2026-06-19 | Add armv7::InstDecoder::in_thumb_mode() method | Samuel Arnold |
| 2026-02-22 | support A1 encoding of several coprocessor instructions + SVC | rva3 |
