| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-07-28 | probably should decide where imm-shifted reg normalization happens | iximeow | |
| 2026-07-28 | Decode the correct number of operands for CMP/CMN (immediate/register) | Grond | |
| This also incidentally fixes an issue where MOV/MVN instructions with a shifted operand could be decoded as if they had 3 operands. | |||
| 2026-07-28 | Fix the handling of reserved bits in uncommon loads/stores | Grond | |
| There's a pattern of load/store instructions that look something like * `ldr<variant> <target registers>, [<base register>, +/- <offset register>]` * `str<variant> <target registers>, [<base register>, +/- <offset register>]` These instructions share a common encoding format, which includes the presence of 4 reserved bits starting at bit 8 in the instruction word. These bits should always be zero, according to `DDI0406C_d_armv7ar_arm.pdf`. However, while this crate did attempt to validate these bits sometimes, the validation was inverted. Instead of checking that the bits were zero, the validation would raise an error if all of the bits were zero! Additionally, some instructions were missing the check and some instructions that did not use the aforementioned encoding scheme incorrectly had the check applied to them. This commit fixes all of the issues I've found along these lines so far. | |||
| 2026-07-28 | Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2 | Grond | |
| 2026-07-28 | Implement the RRX immediate shift type | Grond | |
| 2026-07-28 | Fix the handling of arithmetic register shifts with zero immediates | Grond | |
| 2026-06-19 | Add armv7::InstDecoder::in_thumb_mode() method | Samuel Arnold | |
| 2026-02-22 | support A1 encoding of several coprocessor instructions + SVC | rva3 | |
| initially was "implement MCR/MRC decoding", but expanded to include the whole coprocessor space for completeness, and then SVC is right there too. Neon instructions in this space are still rejected, as neon support is not really there yet. Co-authored-by: iximeow <me@iximeow.net> | |||
| 2026-02-22 | properly display coprocessor higher than 9 | rva3 | |
| 2026-02-22 | rename MCR2/MRC2 to MCR/MRC | rva3 | |
| they share exactly the same encoding, except the high bits for condition the bool indicates if it's A2 encondings which is unconditional | |||
| 2026-02-22 | derive Clone and Copy for armv7 instruction | rva3 | |
| 2025-10-19 | run differential test0.4.0 | iximeow | |
| 2025-10-19 | adjust goodfile to exercise feature matrix more | iximeow | |
| 2025-10-19 | alloc needs yaxpeax-arch alloc too | iximeow | |
| 2025-10-19 | Remove empty format precision specifier | Marijn Schouten | |
| A format precision specifier consisting of a dot and no number actually does nothing and has no specified meaning. Currently this is silently ignored, but it may turn into a warning or error. See rust-lang/rust#131159 and rust-lang/rust#136638 | |||
| 2025-10-19 | update changelog, no 0.3.2 after all | iximeow | |
| 2025-10-19 | Opcode and Operand should be non-exhaustive | iximeow | |
| but exhaustiveness checking is very valuable here, so allow it to be disabled. caveats apply. read the docs in Cargo.toml. | |||
| 2025-10-19 | avoid subtle changes to A64 Opcode enum discriminant choices | iximeow | |
| 2025-10-19 | tag instruction decode fixes, differential test precision | iximeow | |
| 2025-10-19 | fix opcode display for ldg | Martin Fink | |
| 2025-10-19 | visitor-oriented fmt | iximeow | |
| this makes a decode+format benchmark drop from 75s to 14s... (decode is 5s) | |||
| 2025-06-20 | changelog + another inline | iximeow | |
| 2025-06-02 | some armv7 decode helpers are trivial functions but didn't inline | iximeow | |
| both from_u8 and the build function here compiled to truly trivial code: four instructions (mov rdi, rax; cmp 0xlim, rax; jae panic; ret) in the hot path, and constrained register choice on the caller side. inlining these makes for a *smaller* armv7 decoder, on the order of 5kb down from 5.5kb. in the process it also gets about 45% faster (400mb/s to 560mb/s) inlining decode_into, then, really just helps the standalone decoder benchmark case. this moves decode throughput from 560mb/s to 724mb/s. | |||
| 2025-05-25 | support the rest of PAC instructions. compare to a more recent capstone | iximeow | |
| capstone-rs currently binds an old capstone (4.0), where capstone 5.0 is where much of the armv8.2+ implementation was ported over from LLVM. so, differential testing is now pointed to a capstone-rs fork pending the merge of https://github.com/capstone-rust/capstone-rs/pull/172 | |||
| 2025-02-06 | 0.3.10.3.1 | iximeow | |
| 2025-02-06 | actually check no-std configuration does not transitively depend on std | iximeow | |
| 2025-02-04 | Disable bitvec features to fix no_std | Luke Street | |
| 2024-06-25 | update yaxpeax-arch in differential-tests, validate in goodfile | iximeow | |
| 2024-06-25 | 0.3.00.3.0 | iximeow | |
| 2024-06-25 | Bump yaxpeax-arch and bitvec, allow use of deprecated yaxpeax-arch traits, ↵ | novafacing | |
| fix bitvec syntax changes | |||
| 2024-06-25 | 0.2.60.2.6 | iximeow | |
| 2024-06-25 | include udf note in changelog | iximeow | |
| 2024-06-25 | Add support for `udf` | Martin Fink | |
| 2024-03-17 | at least armv7t doesnt panic now, but im very uncertain these are right | iximeow | |
| 2024-03-17 | run non-panicking tests with a horkton of parallelism | iximeow | |
| they run in minute or so now and the thumb mode panics....??? | |||
| 2024-03-17 | armv8 no-panic test is now multithreaded | iximeow | |
| 2024-03-17 | differential test: more refinement on exceptions | iximeow | |
| 2024-03-17 | resolve warnings, make textual disassembly in differential tests a little faster | iximeow | |
| 2024-03-17 | differential tests: RUSTFLAGS on aarch64 note | iximeow | |
| 2024-03-17 | ye olde "const array rebuilt in locals with simd but static is const" issue | iximeow | |
| 2024-03-17 | differential tests: unnecessary mut | iximeow | |
| 2024-03-17 | ah uxtw/h fix introduced warnings | iximeow | |
| 2024-03-17 | differential test: use raw capstone interface to avoid reallocating cs_insn | iximeow | |
| 2024-03-17 | differential test: atomic adds are relaxed, dont need specific ordering | iximeow | |
| 2024-03-17 | fix uxtb/uxth alias being incorrectly applied with x-size registers | iximeow | |
| 2024-03-17 | differential tests: more unneeded special cases | iximeow | |
| 2024-03-17 | differential tests: width-aware immediate parsing | iximeow | |
| 2024-03-17 | when decoding invalid opcodes, return errors. better testing for this ↵ | iximeow | |
| circumstance. | |||
| 2024-03-17 | disassembling sb is fine, tests ensure it happens now | iximeow | |
| 2024-03-17 | capstone also reports msr for some undefined encodings | iximeow | |
 |
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