| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 8 hours | report rounding bit of smmla/smmls | iximeow | |
| 8 hours | fix hvc immediate missing its upper four bits | iximeow | |
| 8 hours | fix ssat/16 second operand off by one, testcases | iximeow | |
| 8 hours | fix issues around unpredictable ldrd and offset printing | iximeow | |
| 8 hours | fix {s,u}xt{h,b}[16] using an immediate to describe their rotates | iximeow | |
| 8 hours | fix mrc/mrc2 use of CRd=15 | iximeow | |
| 2026-08-04 | write condition code *before* .w suffix | iximeow | |
| 2026-08-04 | msr confusion like with mrs.. | iximeow | |
| 2026-08-03 | armv8 thumb-mode hints | iximeow | |
| 2026-08-03 | decode unknown wide hints like any other hints | iximeow | |
| 2026-08-02 | fix swapped rfe{ia,db} and srs{ia,db} | iximeow | |
| 2026-08-02 | fix missing decode of `s` bit for wide shift/rotate ops | iximeow | |
| 2026-08-02 | thumb ldc/stc encodings missed a bit | iximeow | |
| 2026-08-02 | sufficiently advanced SIMD is indistinguishable from coprocessors | iximeow | |
| 2026-08-02 | thumb2 preload improvements | iximeow | |
| 2026-08-02 | thumb SIMD encoding should have returned Incomplete | iximeow | |
| 2026-08-02 | pkhbt/pkhtb bitmask confusion | iximeow | |
| 2026-08-02 | Test Target, fix bogus MRS destinations | iximeow | |
| 2026-08-02 | ldrexd changelog | iximeow | |
| 2026-07-28 | thumb2: fix parallel addition/subtraction, (un)signed | iximeow | |
| 2026-07-28 | fix thumb2 TBH decode: wrong opcode and register-shift operand | Brandon Ros | |
| the T1 TBH arm set Opcode::TBB instead of Opcode::TBH, and built the index operand with bit 4 set in the RegShift raw value. bit 4 is the RegReg selector in RegShift::into_shift, so the mandatory 'lsl #1' index scaling decoded as a register shift 'lsl r0' instead. clear bit 4 so it reads back as the RegImm 'lsl #1' the encoding specifies. verified against binutils objdump: df e8 13 f0 is tbh [pc, r3, lsl #1]. | |||
| 2026-07-28 | fix more thumb2 register data-processing decode bugs | Brandon Ros | |
| - register-controlled shifts (lsl/lsr/asr/ror by register) all decoded as lsl: the shift type was read from hw1[6:5] (always 0 for this form) instead of hw0[6:5] - 32-bit uxt*/sxt* extends read the ror amount from the wrong field (hw1[2:1] scaled by 4 instead of hw1[5:4] scaled by 8), so a no-rotation extend came back as ror #4; rotation of 0 is now omitted - sxtab was decoded as sxtah (wrong opcode table entry) all cases verified against binutils objdump | |||
| 2026-07-28 | fix several thumb2 decode bugs | Brandon Ros | |
| - 32-bit store encodings with the imm12 bit (bit 23) set were decoded as the register-offset form when imm12 < 64, or as strbt/strht/strt when imm12 was 0xExx. bit 23 set always means the imm12 form. - movw/movt packed imm4 at bit 16 instead of bit 12, producing 20-bit immediates (e.g. 0xf0005 instead of 0xf005) - mvn (immediate) was decoded as mov, dropping the bitwise not - ror (immediate) was decoded as asr all cases verified against binutils objdump | |||
| 2026-07-28 | Decode the correct number of operands for TST/TEQ (immediate/register) | Grond | |
| 2026-07-28 | Decode the correct number of operands for CMP/CMN (immediate/register) | Grond | |
| This also incidentally fixes an issue where MOV/MVN instructions with a shifted operand could be decoded as if they had 3 operands. | |||
| 2026-07-28 | Fix the handling of reserved bits in uncommon loads/stores | Grond | |
| There's a pattern of load/store instructions that look something like * `ldr<variant> <target registers>, [<base register>, +/- <offset register>]` * `str<variant> <target registers>, [<base register>, +/- <offset register>]` These instructions share a common encoding format, which includes the presence of 4 reserved bits starting at bit 8 in the instruction word. These bits should always be zero, according to `DDI0406C_d_armv7ar_arm.pdf`. However, while this crate did attempt to validate these bits sometimes, the validation was inverted. Instead of checking that the bits were zero, the validation would raise an error if all of the bits were zero! Additionally, some instructions were missing the check and some instructions that did not use the aforementioned encoding scheme incorrectly had the check applied to them. This commit fixes all of the issues I've found along these lines so far. | |||
| 2026-07-28 | Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2 | Grond | |
| 2026-07-28 | Implement the RRX immediate shift type | Grond | |
| 2026-07-28 | Fix the handling of arithmetic register shifts with zero immediates | Grond | |
| 2026-06-19 | Add armv7::InstDecoder::in_thumb_mode() method | Samuel Arnold | |
| 2026-02-22 | support A1 encoding of several coprocessor instructions + SVC | rva3 | |
| initially was "implement MCR/MRC decoding", but expanded to include the whole coprocessor space for completeness, and then SVC is right there too. Neon instructions in this space are still rejected, as neon support is not really there yet. Co-authored-by: iximeow <me@iximeow.net> | |||
| 2026-02-22 | derive Clone and Copy for armv7 instruction | rva3 | |
| 2025-10-19 | update changelog, no 0.3.2 after all | iximeow | |
| 2025-10-19 | tag instruction decode fixes, differential test precision | iximeow | |
| 2025-06-20 | changelog + another inline | iximeow | |
| 2025-02-06 | 0.3.10.3.1 | iximeow | |
| 2024-06-25 | 0.3.00.3.0 | iximeow | |
| 2024-06-25 | include udf note in changelog | iximeow | |
| 2024-03-09 | 0.2.50.2.5 | iximeow | |
| 2023-11-02 | another changelog update, this time actually followed by a release... | iximeow | |
| 2023-04-25 | prepare changelog updates | iximeow | |
| 2022-01-02 | 0.2.3 | iximeow | |
| 2022-01-02 | fix docs typo0.2.2 | iximeow | |
| 2022-01-02 | 0.2.10.2.1 | iximeow | |
| 2022-01-02 | document the crate | iximeow | |
| 2022-01-01 | 0.1.4 | iximeow | |
| 2021-09-28 | do not publish crates with compilation warnings (bump for 0.1.3 also)0.1.3 | iximeow | |
| 2021-09-28 | handle another unintended panic in display impl | iximeow | |
| 2021-09-28 | fix various armv8 and armv8 panics that should be Err. | iximeow | |
| in fact the decoder should _never_ panic. included here are tests that cover the entire 32-bit instruction space and ensure that decoding and display do not panic. these tests run uncomfortably slowly (1168s to decode the 4b "instruction" sequences on my desktop), but verify that panics are no longer an issue. | |||
| 2021-07-21 | fix DecodeError impl on builds using yaxpeax-arch+std0.1.1 | iximeow | |
 |
index : yaxpeax-arm | |
| yaxpeax arm decoder |
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