| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-07-28 | Decode the correct number of operands for TST/TEQ (immediate/register) | Grond | |
| 2026-07-28 | Decode the correct number of operands for CMP/CMN (immediate/register) | Grond | |
| This also incidentally fixes an issue where MOV/MVN instructions with a shifted operand could be decoded as if they had 3 operands. | |||
| 2026-07-28 | Fix the handling of reserved bits in uncommon loads/stores | Grond | |
| There's a pattern of load/store instructions that look something like * `ldr<variant> <target registers>, [<base register>, +/- <offset register>]` * `str<variant> <target registers>, [<base register>, +/- <offset register>]` These instructions share a common encoding format, which includes the presence of 4 reserved bits starting at bit 8 in the instruction word. These bits should always be zero, according to `DDI0406C_d_armv7ar_arm.pdf`. However, while this crate did attempt to validate these bits sometimes, the validation was inverted. Instead of checking that the bits were zero, the validation would raise an error if all of the bits were zero! Additionally, some instructions were missing the check and some instructions that did not use the aforementioned encoding scheme incorrectly had the check applied to them. This commit fixes all of the issues I've found along these lines so far. | |||
| 2026-07-28 | Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2 | Grond | |
| 2026-07-28 | Implement the RRX immediate shift type | Grond | |
| 2026-07-28 | Fix the handling of arithmetic register shifts with zero immediates | Grond | |
| 2026-06-19 | Add armv7::InstDecoder::in_thumb_mode() method | Samuel Arnold | |
| 2026-02-22 | support A1 encoding of several coprocessor instructions + SVC | rva3 | |
| initially was "implement MCR/MRC decoding", but expanded to include the whole coprocessor space for completeness, and then SVC is right there too. Neon instructions in this space are still rejected, as neon support is not really there yet. Co-authored-by: iximeow <me@iximeow.net> | |||
| 2026-02-22 | derive Clone and Copy for armv7 instruction | rva3 | |
| 2025-10-19 | update changelog, no 0.3.2 after all | iximeow | |
| 2025-10-19 | tag instruction decode fixes, differential test precision | iximeow | |
| 2025-06-20 | changelog + another inline | iximeow | |
| 2025-02-06 | 0.3.10.3.1 | iximeow | |
| 2024-06-25 | 0.3.00.3.0 | iximeow | |
| 2024-06-25 | include udf note in changelog | iximeow | |
| 2024-03-09 | 0.2.50.2.5 | iximeow | |
| 2023-11-02 | another changelog update, this time actually followed by a release... | iximeow | |
| 2023-04-25 | prepare changelog updates | iximeow | |
| 2022-01-02 | 0.2.3 | iximeow | |
| 2022-01-02 | fix docs typo0.2.2 | iximeow | |
| 2022-01-02 | 0.2.10.2.1 | iximeow | |
| 2022-01-02 | document the crate | iximeow | |
| 2022-01-01 | 0.1.4 | iximeow | |
| 2021-09-28 | do not publish crates with compilation warnings (bump for 0.1.3 also)0.1.3 | iximeow | |
| 2021-09-28 | handle another unintended panic in display impl | iximeow | |
| 2021-09-28 | fix various armv8 and armv8 panics that should be Err. | iximeow | |
| in fact the decoder should _never_ panic. included here are tests that cover the entire 32-bit instruction space and ensure that decoding and display do not panic. these tests run uncomfortably slowly (1168s to decode the 4b "instruction" sequences on my desktop), but verify that panics are no longer an issue. | |||
| 2021-07-21 | fix DecodeError impl on builds using yaxpeax-arch+std0.1.1 | iximeow | |
| 2020-12-06 | bump to 0.0.6 and fix markdown0.0.6 | iximeow | |
| 2020-12-06 | bump version to 0.0.5 update documentation some0.0.5 | iximeow | |
| add some keywords to the crate. this is a first for yaxpeax | |||
| 2020-03-15 | bump version to 0.0.3 and add a changelog | iximeow | |
 |
index : yaxpeax-arm | |
| yaxpeax arm decoder |
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