aboutsummaryrefslogtreecommitdiff
path: root/test
AgeCommit message (Collapse)Author
2022-01-02get test situation in orderiximeow
2022-01-02document the crateiximeow
2022-01-01fix test expectationsiximeow
2022-01-01capstone/yax differences, test pac more comprehensivelyiximeow
2022-01-01more inconvenient test case handlingiximeow
2022-01-01test expectation cleanupiximeow
2021-12-31more pac instructions, fmov fixesiximeow
2021-12-31fix more invalid rejects, misdecodes, test casesiximeow
2021-12-31shift/sm3ss fixesiximeow
2021-12-31sshll is weirdiximeow
2021-12-31pac, cfi, other misc cleanup, notes and todosiximeow
2021-12-30many many MORE one-off fixes from differential testingiximeow
2021-12-29more missed tables and manual compatiximeow
2021-12-29more misc fixesiximeow
2021-12-29more armv8.1 instructions, fix cas operand checkiximeow
2021-12-29and sve should error for nowiximeow
2021-12-29stxrb memory operand erroriximeow
2021-12-29cas and sme/sve stubiximeow
2021-12-28re-enable exhaustive panic testsiximeow
2021-12-27fix variable-width index, more fp16 instructionsiximeow
2021-12-27movi/mvni scalar/vectoriximeow
2021-12-27fcmp/fcmpe fixesiximeow
2021-12-27vector fabs/fcm*iximeow
2021-12-27vector x indexed fmla,fmls,fmuliximeow
2021-12-27Advanced SIMD Extractiximeow
2021-12-27fix Advanced SIMD Scalar Three Sameiximeow
2021-12-27more tests that were inaccurateiximeow
2021-12-27significantly expand simd support, correct tests for aliasingiximeow
2021-12-04ignore non-panic tests for nowiximeow
2021-11-20more simd supportiximeow
2021-11-07floating point mov, several data processing ops, compareiximeow
2021-10-31SIMD load/store (multiple structure)iximeow
in addition to the decoding support, objdump reporting of `{}` selection of multiple registers seems to be inconsistent. stick to the manual's preferred `{v1, v2, v3, v4}` nomenclature instead of `{v1-v4}`. reorder a few tests in test_openblas_simd_loadstore to group instructions by decode category
2021-10-30support ldp/stp/others, preindex writeback is optionaliximeow
2021-10-30support simd load/store (single structure)iximeow
2021-10-26add many test cases from openblas, ldnp, stnpiximeow
2021-10-24normalize a bit more consistently in instruction displayiximeow
2021-10-21data processing (three source)iximeow
2021-10-21data processing instructions (one source)iximeow
2021-10-21ccm{n,p}iximeow
2021-09-28handle another unintended panic in display impliximeow
2021-09-28fix various armv8 and armv8 panics that should be Err.iximeow
in fact the decoder should _never_ panic. included here are tests that cover the entire 32-bit instruction space and ensure that decoding and display do not panic. these tests run uncomfortably slowly (1168s to decode the 4b "instruction" sequences on my desktop), but verify that panics are no longer an issue.
2021-09-26fix unimplemented code paths panicking as unreachableiximeow
only in a64 decoding really; there wasn't an "Incomplete" error at the time, but now there is.
2021-09-14Fix display of post-index writeback operandsJonas Schievink
2021-07-06update yaxpeax_arch and bump version to 0.1.00.1.0iximeow
2020-12-06TODONE: adr with add/subtracted offsetiximeow
instead of trying to shoehorn in `adr reg, label` syntax like the manual requests, it's much easier to just describe these as `{add, sub} reg, pc, offset` and potentially rewrite `pc, offset` as an `adr reg, label` if a higher-level tool has that kind of information available.
2020-12-06warning cleanup (test edition)iximeow
add in some simd tests for future neon decoding. these tests are drawn from capstone and may need some subsequent cleanup
2020-12-06add ldc/sdc instructions and a slew of 32b thumb2 testsiximeow
2020-12-06fix more incomplete cases, report arm instruction length properlyiximeow
2020-12-06fix some 32-bit thumb2 instructions, hook up .w, `s`, and a few typosiximeow
mostly confusion of pre/post-increment, operand widths, immediate widths, things of that nature
2020-12-06add thumb/thumb2 decodingiximeow
16-bit instructions only, for now
generated by cgit v1.1 at 2024-11-22 01:38:46 +0000