yaxpeax-arm - yaxpeax arm decoder

Age	Commit message (Collapse)	Author
2026-07-28	Decode the correct number of operands for CMP/CMN (immediate/register)	Grond
	This also incidentally fixes an issue where MOV/MVN instructions with a shifted operand could be decoded as if they had 3 operands.
2026-07-28	Fix the handling of reserved bits in uncommon loads/stores	Grond
	There's a pattern of load/store instructions that look something like * `ldr<variant> <target registers>, [<base register>, +/- <offset register>]` * `str<variant> <target registers>, [<base register>, +/- <offset register>]` These instructions share a common encoding format, which includes the presence of 4 reserved bits starting at bit 8 in the instruction word. These bits should always be zero, according to `DDI0406C_d_armv7ar_arm.pdf`. However, while this crate did attempt to validate these bits sometimes, the validation was inverted. Instead of checking that the bits were zero, the validation would raise an error if all of the bits were zero! Additionally, some instructions were missing the check and some instructions that did not use the aforementioned encoding scheme incorrectly had the check applied to them. This commit fixes all of the issues I've found along these lines so far.
2026-07-28	Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2	Grond

2026-07-28	Implement the RRX immediate shift type	Grond

2026-07-28	Fix the handling of arithmetic register shifts with zero immediates	Grond

2026-02-22	support A1 encoding of several coprocessor instructions + SVC	rva3
	initially was "implement MCR/MRC decoding", but expanded to include the whole coprocessor space for completeness, and then SVC is right there too. Neon instructions in this space are still rejected, as neon support is not really there yet. Co-authored-by: iximeow <me@iximeow.net>
2026-02-22	properly display coprocessor higher than 9	rva3

2023-01-31	fix 24-bit branch immediate decoding	jam1garner

2022-01-02	get test situation in order	iximeow