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5 hoursfix ssat/16 second operand off by one, testcasesiximeow
5 hoursfix issues around unpredictable ldrd and offset printingiximeow
5 hoursfix {s,u}xt{h,b}[16] using an immediate to describe their rotatesiximeow
5 hoursfix mrc/mrc2 use of CRd=15iximeow
5 hoursmore lining up differential testsiximeow
2026-08-06cdp/mrc/mcr opc1 is wider than display knowsiximeow
2026-08-04write condition code *before* .w suffixiximeow
2026-08-04msr confusion like with mrs..iximeow
2026-08-03armv8 thumb-mode hintsiximeow
2026-08-03decode unknown wide hints like any other hintsiximeow
2026-08-02fix swapped rfe{ia,db} and srs{ia,db}iximeow
2026-08-02fix missing decode of `s` bit for wide shift/rotate opsiximeow
2026-08-02thumb ldc/stc encodings missed a bitiximeow
2026-08-02thumb2 preload improvementsiximeow
2026-08-02pkhbt/pkhtb bitmask confusioniximeow
2026-08-02Test Target, fix bogus MRS destinationsiximeow
2026-08-02thumb mrs/msr first operand was wildly wrongiximeow
2026-07-28temp, armv8-thumbiximeow
2026-07-28thumb2: fix parallel addition/subtraction, (un)signediximeow
2026-07-28thumb: when nonconforming, allow it/cond=1111 like capstoneiximeow
2026-07-28differential test should tolerate a few more differencesiximeow
2026-07-28untangle some nonconforming ld/st formsiximeow
2026-07-28lsl/mov aliasingiximeow
2026-07-28differential testing wipiximeow
2026-07-28fix thumb2 TBH decode: wrong opcode and register-shift operandBrandon Ros
2026-07-28fix more thumb2 register data-processing decode bugsBrandon Ros
2026-07-28fix several thumb2 decode bugsBrandon Ros
2026-07-28Do not add an 's' when outputing opcodes that always set flagsGrond
2026-07-28Decode the correct number of operands for TST/TEQ (immediate/register)Grond
2026-07-28Simplify decoding of register-shifted-register data-processing instructionsGrond
2026-07-28Decode the correct number of operands for CMP/CMN (immediate/register)Grond
2026-07-28Fix the handling of reserved bits in uncommon loads/storesGrond
2026-07-28Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2Grond
2026-07-28Implement the RRX immediate shift typeGrond
2026-07-28Fix the handling of arithmetic register shifts with zero immediatesGrond
2026-02-22support A1 encoding of several coprocessor instructions + SVCrva3
2026-02-22properly display coprocessor higher than 9rva3
2023-01-31fix 24-bit branch immediate decodingjam1garner
2022-09-29Add a test for issue #3Mitchell Johnson
2022-09-29Add some additional 32-bit thumb branch decode test casesMitchell Johnson
2022-09-29Fix 32-bit conditional thumb branchesMitchell Johnson
2022-09-29Fix negative unconditional 16-bit thumb branchesMitchell Johnson
2022-09-29Fix 32-bit Thumb unconditional branch decodingMitchell Johnson
2022-01-02get test situation in orderiximeow
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