| Age | Commit message (Expand) | Author |
|---|---|---|
| 2026-07-28 | Decode the correct number of operands for CMP/CMN (immediate/register) | Grond |
| 2026-07-28 | Fix the handling of reserved bits in uncommon loads/stores | Grond |
| 2026-07-28 | Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2 | Grond |
| 2026-07-28 | Implement the RRX immediate shift type | Grond |
| 2026-07-28 | Fix the handling of arithmetic register shifts with zero immediates | Grond |
| 2026-02-22 | support A1 encoding of several coprocessor instructions + SVC | rva3 |
| 2026-02-22 | properly display coprocessor higher than 9 | rva3 |
| 2023-01-31 | fix 24-bit branch immediate decoding | jam1garner |
| 2022-09-29 | Add a test for issue #3 | Mitchell Johnson |
| 2022-09-29 | Add some additional 32-bit thumb branch decode test cases | Mitchell Johnson |
| 2022-09-29 | Fix 32-bit conditional thumb branches | Mitchell Johnson |
| 2022-09-29 | Fix negative unconditional 16-bit thumb branches | Mitchell Johnson |
| 2022-09-29 | Fix 32-bit Thumb unconditional branch decoding | Mitchell Johnson |
| 2022-01-02 | get test situation in order | iximeow |
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