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This also incidentally fixes an issue where MOV/MVN instructions with a
shifted operand could be decoded as if they had 3 operands.
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There's a pattern of load/store instructions that look something like
* `ldr<variant> <target registers>,
[<base register>, +/- <offset register>]`
* `str<variant> <target registers>,
[<base register>, +/- <offset register>]`
These instructions share a common encoding format, which includes the
presence of 4 reserved bits starting at bit 8 in the instruction word.
These bits should always be zero, according to
`DDI0406C_d_armv7ar_arm.pdf`. However, while this crate did attempt to
validate these bits sometimes, the validation was inverted. Instead of
checking that the bits were zero, the validation would raise an error if
all of the bits were zero! Additionally, some instructions were missing
the check and some instructions that did not use the aforementioned
encoding scheme incorrectly had the check applied to them.
This commit fixes all of the issues I've found along these lines so far.
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initially was "implement MCR/MRC decoding", but expanded to include the
whole coprocessor space for completeness, and then SVC is right there
too.
Neon instructions in this space are still rejected, as neon support is
not really there yet.
Co-authored-by: iximeow <me@iximeow.net>
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Correct the shift used to select condition bits and correctly compute the
branch offset.
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Sign extension shift had an off-by-one error so the sign bit was not being
properly extended.
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T4 encodings of unconditional branches were not being interpreted correctly
(#6), and 32-bit bl/blx instructions were similarly incorrect. Correct the bits
selected for op1 and op2 and handle the slightly-unusual i1/i2 sign bit xor for
these instructions.
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