path: root/src/lib.rs

//! # `yaxpeax-power`, a decoder for the `power` instruction set family.
//!
//! this covers the Power ISA up through v3.1, as well as settings to decode instructions as
//! PowerPC. the interplay between POWER, PowerPC, and the Power ISA are somewhat historically
//! interesting, and as the instruction sets are interrelated, the decoder here strives to support
//! the whole lineage through which they are related.
//!
//! a whirlwind tour (i think accurate, but i'm not totally sure!):
//! * In The Beginning there was the RS/6000, later also called "POWER1".
//! * later, POWER2 came to market. this was, so far as i know, architecturally very similar, and
//!   came alongside the still-similar PowerPC 601. it's not clear to me how the 601 relates to the
//!   PowerPC ISA, PowerPC 603, and later PowerPC processors.
//! * POWER3 involves some elements of PowerPC, but i'm not sure what (yet?).
//! * POWER4 and PowerPC are roughly overlapping. there are revisions here and it's not
//!   clear to me when 2.0 and 2.01 happen in relation to particular product naming.
//! * POWER5 is formalized in the Power ISA v2.02 book
//! * subsequent revisions of the Power 2 ISA are implemented in some later "PowerPC" processor
//!   models
//! * subsequent revisions of the Power 2 ISA *also* are implemented in POWER6, POWER7, POWER8.
//! * Power ISA 3.0 is implemented in POWER9, as well as OpenPOWER and friends.
//! * Power ISA 3.1 is implemented in POWER10, and POWER11.
//! * and who knows what POWER12(?) will bring! not me in 2026.
//!
//! so: along the POWER1 to POWER12 lineage, architectures are backwards compatible ... for the
//! most part. there are some divergences where instructions that were valid in POWER1 were dropped
//! in moving to PowerPC and what became Power v2.0, but many moved with only different mnemonics.
//! from v2.0 onwards, though, backwards compatibility reigns supreme.
//!
//! `yaxpeax-power` configures the disassembler based on requested Power ISA revision, and
//! provides aliases for particular processors where appropriate.
//!
//! ## usage
//!
//! `yaxpeax-power` usage demo:
//! ```
//! use yaxpeax_arch::Decoder;
//!
//! let decoder = yaxpeax_power::InstDecoder::default();
//! let expected = "lvewx vr0, 0, r10";
//! let data = [0x7c, 0x00, 0x50, 0x8e];
//! let mut reader = yaxpeax_arch::U8Reader::new(&data[..]);
//! let inst = decoder.decode(&mut reader).unwrap();
//! assert_eq!(format!("{}", inst), expected);
//!
//! // or, in fewer words:
//! let inst = decoder.decode_slice(&data).unwrap();
//! assert_eq!(format!("{}", inst), expected);
//! ```

#![no_std]
#![deny(missing_docs)]

use core::fmt;

use yaxpeax_arch::{
    Decoder, Arch, Reader, AddressDiff, ReadError, LengthedInstruction,
};

#[cfg(feature = "fmt")]
/// structs and functions useful for either printing a decoded instruction, custom logic to control
/// instruction formatting, or implementation of custom `DisplaySink` for `yaxpeax-power`
/// instructions.
pub mod display;
#[cfg(feature = "fmt")]
pub use display::{compute_branch_mnemonic, AbsoluteAddressFormatter, DisplayRules, NoAliasRules};

mod alias;
pub use alias::{AliasOp, InstructionAlias, OpcodeAlias};

/// the `Power` struct and [`Arch`] impl'd on it describe both the old 32-bit implementations as
/// well as 64-bit implementations and their 32-bit modes. this is mostly for expedience;
/// duplicating [`Instruction`] and impls on it for the sake of a more precise `Opcode` implies a
/// lot of library duplication for relatively little gain. (the library needs to document which
/// instructions can be decoded in which ISA revisions anyway for all the 2.0-and-later additions,
/// so adding some documentation about "before-PowerPC" is already on the docket)
///
/// this is mainly confusing for `Power` having a "`u64`" address size, even when decoding Power
/// ISA instructions for 32-bit ISA revisions (namely, "Power v1.0" as seen in POWER1/POWER2). if
/// you're in the extraordinarily rare set of users who might be interested in that distinction,
/// this is why the library is the way that it is. and if i've modeled the Power ISA incorrectly,
/// please say hello!
pub struct Power {}

impl Arch for Power {
    /// Power is bi-endian, but so far as i can tell *defaults* to big-endian and first-party
    /// software before the Linux transition to ppc64le *seems* to be big-endian also?
    type Word = yaxpeax_arch::U32be;
    type Address = u64;
    type Instruction = Instruction;
    type DecodeError = DecodeError;
    type Decoder = InstDecoder;
    type Operand = Operand;
}

/// the kinds of errors possibly encountered in trying to decode a `power` instruction
#[derive(Debug, PartialEq, Copy, Clone)]
pub enum DecodeError {
    /// the input was insufficient to decode a full instruction (that is, there were not four bytes
    /// available).
    ExhaustedInput,
    /// the instruction encodes an opcode that is not valid.
    InvalidOpcode,
    /// the instruction encodes an operand that is not valid.
    InvalidOperand,
    /// `yaxpeax-power` doesn't know how to decode this, but it may be a valid instruction. the
    /// instruction decoder is not complete, sorry. :(
    IncompleteDecoder,
}

impl fmt::Display for DecodeError {
    fn fmt(&self, f:  &mut fmt::Formatter) -> fmt::Result {
        use yaxpeax_arch::DecodeError;
        f.write_str(self.description())
    }
}

#[cfg(feature = "std")]
extern crate std;
#[cfg(feature = "std")]
impl std::error::Error for DecodeError {
    fn description(&self) -> &str {
        <Self as yaxpeax_arch::DecodeError>::description(self)
    }
}

impl From<ReadError> for DecodeError {
    fn from(_e: ReadError) -> DecodeError {
        DecodeError::ExhaustedInput
    }
}

impl yaxpeax_arch::DecodeError for DecodeError {
    fn data_exhausted(&self) -> bool { self == &DecodeError::ExhaustedInput }
    fn bad_opcode(&self) -> bool { self == &DecodeError::InvalidOpcode }
    fn bad_operand(&self) -> bool { self == &DecodeError::InvalidOperand }
    fn description(&self) -> &'static str {
        match self {
            DecodeError::ExhaustedInput => "exhausted input",
            DecodeError::InvalidOpcode => "invalid opcode",
            DecodeError::InvalidOperand => "invalid operand",
            DecodeError::IncompleteDecoder => "incomplete decoder",
        }
    }
}

impl yaxpeax_arch::Instruction for Instruction {
    fn well_defined(&self) -> bool { true }
}

/// a `power` instruction decoder.
///
/// this can be configured to decode instruction for any supported step along the Power ISA lineage
/// via [`IsaVersion`]
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash)]
pub struct InstDecoder {
    /// what version of the Power ISA does the processor support?
    version: IsaVersion,

    /// is the processor operating in big-endian mode? this defaults to `true`, but can be
    /// dynamically changed by writing to an MSR.
    is_be: bool,
}

/// opcode 4 has mutually-incompatible interpretations (either vector/LMA or signal processing
/// extensions). so, which do we get from the current decoder settings?
#[allow(dead_code)]
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash)]
enum Opc4Mode {
    /// aka "VMX", present in Power v2.06+ and Cell PPE.
    AltiVec,
    /// the interesting quirk mode of VMX used by Xenon with 128 vector registers.
    VMX128,
    /// the later VSX extensions on the vector ISA.
    VSX,
    /// "Paired Singles", the paired single extension used in Gekko.
    PS,
    /// "Signal Processing", several categories of instructions included in embedded Power
    /// implementations, which were mutually exclusive with AltiVec encodings under opcode 4.
    SP,
}

/// opcode 39 also has mutually-incompatible interpretations.  so, which do we get from the current
/// decoder settings?
#[allow(dead_code)]
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash)]
enum Opc39Mode {
    /// interpret opcode 39 as Gekko would.
    Gekko,
    /// interpret opcode 39 as a Power v2.05+ system would (`lfdp`)
    DFP,
    /// interpret opcode 39 as a POWER2 CPU would (`lfqu`)
    POWER2,
}

/// opcode 3C also has mutually-incompatible interpretations (`psq_st` or VSX, depending on ISA).
/// so, which do we get from the current decoder settings?
#[allow(dead_code)]
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash)]
enum Opc3cMode {
    /// interpret opcode 3C as Gekko would, a `psq_st`.
    Gekko,
    /// the later VSX extensions on the vector ISA.
    VSX,
    /// interpret opcode 3C as a POWER2 CPU would (`stfq`)
    POWER2,
}

/// opcode 3D also has mutually-incompatible interpretations (`psq_stu` or VSX, depending on ISA).
/// so, which do we get from the current decoder settings?
#[allow(dead_code)]
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash)]
enum Opc3dMode {
    /// interpret opcode 3D as Gekko would, a `psq_stu`.
    Gekko,
    /// the later VSX extensions on the vector ISA.
    VSX,
    /// the liminal space after 2.05 which defined `stfdp` for opcode 3D, and before the 3.0-era
    /// additions to VSX which defined additional XO fields.
    STFDP,
    /// interpret opcode 3D as a POWER2 CPU would (`stfqu`)
    POWER2,
}

impl InstDecoder {
    /// configure this `InstDecoder` to decode words as a big-endian processor.
    pub fn with_be(mut self, big_endian: bool) -> Self {
        self.is_be = big_endian;
        self
    }

    /// an `InstDecoder` suitably configured for decoding a `pp64le` binary, as found around
    /// Linux-related software targeting POWER8 and later.
    ///
    /// this is shorthand for selecting `IsaVersion::V207` and `with_be(false)`.
    pub fn ppc64le() -> Self {
        InstDecoder::for_cpu(IsaVersion::V2_07).with_be(false)
    }

    fn opc4_mode(&self) -> Option<Opc4Mode> {
        // default to VSX as the "v2.06 and later default"
        if self.version == IsaVersion::Xenon {
            Some(Opc4Mode::VMX128)
        } else if self.version == IsaVersion::Gekko {
            Some(Opc4Mode::PS)
        } else if self.version == IsaVersion::All || self.version.supports(IsaConstraint::VSX) {
            Some(Opc4Mode::VSX)
        } else if self.version.supports(IsaConstraint::AltiVec) {
            Some(Opc4Mode::AltiVec)
        } else {
            None
        }
    }

    fn opc39_mode(&self) -> Option<Opc39Mode> {
        if self.version == IsaVersion::Gekko {
            Some(Opc39Mode::Gekko)
        } else if self.version == IsaVersion::All || self.version.supports(IsaConstraint::PowerIsa205) {
            Some(Opc39Mode::DFP)
        } else if self.version == IsaVersion::RIOS2 {
            Some(Opc39Mode::POWER2)
        } else {
            None
        }
    }

    fn opc3c_mode(&self) -> Option<Opc3cMode> {
        if self.version == IsaVersion::Gekko {
            Some(Opc3cMode::Gekko)
        } else if self.version == IsaVersion::All || self.version.supports(IsaConstraint::VSX) {
            Some(Opc3cMode::VSX)
        } else if self.version == IsaVersion::RIOS2 {
            Some(Opc3cMode::POWER2)
        } else {
            None
        }
    }

    fn opc3d_mode(&self) -> Option<Opc3dMode> {
        if self.version == IsaVersion::Gekko {
            Some(Opc3dMode::Gekko)
        } else if self.version == IsaVersion::All || self.version.supports(IsaConstraint::VSX) {
            Some(Opc3dMode::VSX)
        } else if self.version.supports(IsaConstraint::PowerIsa205) {
            Some(Opc3dMode::STFDP)
        } else if self.version == IsaVersion::RIOS2 {
            Some(Opc3dMode::POWER2)
        } else {
            None
        }
    }
}

impl Default for InstDecoder {
    fn default() -> Self {
        Self {
            version: IsaVersion::All,
            is_be: true
        }
    }
}

/// TODO: this probably could use additional per-processor definitions, maybe?
/// >
/// > These forms of the mtcrf and mfcr instructions are intended to
/// > replace the old forms of the instructions (the forms shown in page
/// > 85), which will eventually be phased out of the architecture. The
/// > new forms are backward compatible with most processors that comply
/// > with versions of the architecture that precede Version 2.00. On
/// > those processors, the new forms are treated as the old forms.
/// >
/// > However, on some processors that comply with versions of the
/// > architecture that precede Version 2.00 the new forms may be treated
/// > as follows: (illegal instruction handler, or undefined)
#[allow(non_camel_case_types)]
#[allow(missing_docs)]
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash)]
pub enum IsaVersion {
    /// the PowerPC implementation used in the Nintendo GameCube. additionally this `IsaVersion`
    /// describes Broadway, the PowerPC implementation used in the Nintendo Wii.
    Gekko,
    /// the PowerPC implementation used in the Sony PlayStation 3.
    ///
    /// specifically, this describes the PPU, or Power Processor Unit, in contrast to the
    /// Synergistic Processor Unit (SPU) also present in the Cell processor.
    Cell,
    /// the PowerPC implementation used in the Microsoft Xbox 360.
    Xenon,
    /// the specific Power implementation used in the move of AS/400 to a Power-based processor.
    /// this is also called "Power AS" or "PowerPC AS", and in some manuals also is mentioned as
    /// "Power A".
    Amazon,
    /// the PowerPC e500 core, which among other details included BTB locking instructions.
    e500,
    /// the PowerPC e500mc core, which (in addition to e500) includes `Embedded.Decorated Storage`.
    e500mc,
    /// the Power ISA implemented by POWER1 processors in the early RS/6000 series.
    RIOS,
    /// the Power ISA implemented by POWER2 processors later in the RS/6000 series.
    RIOS2,
    /// the Power ISA as supported by initial 32-bit PowerPC implementations.
    ///
    /// this is not quite POWER4, as the first PowerPC implementations slightly predated additions
    /// in POWER4 (and POWER3!)
    PowerPC,
    /// WIP: whatever POWER3 actually implements. frankenstein powerpc/power2 isa?
    V1_99,
    /// it is theoretically possible that Power v2.0 and v2.01 implementations may have been
    /// 32-bit.
    V2_0_32b,
    V2_01_32b,
    /// Power v2.0 as present in POWER4, or PowerPC 970, were 64-bit.
    V2_0,
    V2_01,
    V2_02,
    V2_03,
    V2_04,
    V2_05,
    V2_06,
    /// the IBM A2 processor (used in Blue Gene/Q). this processor includes instructions in the
    /// implementation-specific region of opcode space. documentation for this processor comes from
    /// `A2 Processor User's Manual for Blue Gene/Q`, retrieved from
    /// <https://wiki.alcf.anl.gov/parts/images/c/cf/A2.pdf> via Wayback Machine
    /// snapshot 01 Dec 2020, `sha256: 72294cf3315ab8b6e0b5b1c436c85bb0b81c2b7acb8e72899873f3a479398973`
    A2,
    V2_07,
    /// POWER9
    V3_0,
    V3_1,
    /// a best-effort interpretation of "decode as many opcodes as have ever been implemented in
    /// any Power processor ever". some byte sequences may have been repurposed with different
    /// interpretations across the ages, so while resulting programs "probably" make sense, they
    /// may be bogus!
    All,
}

impl IsaVersion {
    fn includes_ppc(&self) -> bool {
        match self {
            IsaVersion::RIOS |
            IsaVersion::RIOS2 => false,
            _ => true,
        }
    }

    fn supports(&self, constraint: IsaConstraint) -> bool {
        if *self == IsaVersion::All {
            return true;
        }

        match constraint {
            IsaConstraint::All => true,
            IsaConstraint::LE_POWER2 => {
                // beware: POWER2 is not V2.0! 2.0 was contemporaneous with ~POWER4.
                static LE_POWER2: &'static [IsaVersion] = &[
                    IsaVersion::RIOS, IsaVersion::RIOS2, IsaVersion::V1_99,
                ];
                LE_POWER2.contains(&self)
            }
            IsaConstraint::Fpu => {
                *self == IsaVersion::All ||
                    (*self != IsaVersion::e500 &&
                        (*self == IsaVersion::RIOS || *self == IsaVersion::RIOS2 || self.supports(IsaConstraint::Ppc)))
            }
            // the RS/6000 manual says there's nothing under opcode 59, so no single-precision
            // floats
            IsaConstraint::FpuNoSingle => {
                *self == IsaVersion::All ||
                    (*self != IsaVersion::e500 &&
                        self.supports(IsaConstraint::Ppc))
            }
            IsaConstraint::Isel => {
                // TODO: binutils says many other older POWER implementations support `isel` too
                self.supports(IsaConstraint::PowerIsa206) ||
                    *self == IsaVersion::A2 ||
                    *self == IsaVersion::e500
            }
            IsaConstraint::Btb => {
                *self == IsaVersion::e500
            }
            IsaConstraint::Xenon => {
                *self == IsaVersion::Xenon
            }
            IsaConstraint::Gekko => {
                *self == IsaVersion::Gekko
            }
            IsaConstraint::CellOrXenon => {
                *self == IsaVersion::Cell || *self == IsaVersion::Xenon
            }
            IsaConstraint::Ppc => {
                static PPC_VERSIONS: &'static [IsaVersion] = &[
                    IsaVersion::Amazon, IsaVersion::e500, IsaVersion::e500mc,
                    IsaVersion::Xenon, IsaVersion::Cell, IsaVersion::Gekko,
                    IsaVersion::A2,
                    // v2.05 was standardized in 2007, well after Xenon and Cell, so they are
                    // conspicuously missing here!
                    IsaVersion::PowerPC, IsaVersion::V1_99,
                    IsaVersion::V2_0_32b, IsaVersion::V2_01_32b,
                    IsaVersion::V2_0, IsaVersion::V2_01,
                    IsaVersion::V2_02, IsaVersion::V2_03, IsaVersion::V2_04,
                    IsaVersion::V2_05, IsaVersion::V2_06,
                    IsaVersion::A2,
                    IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1
                ];
                PPC_VERSIONS.contains(&self)
            }
            IsaConstraint::Slb => {
                *self == IsaVersion::Amazon ||
                    (*self != IsaVersion::Xenon && *self != IsaVersion::Gekko && self.supports(IsaConstraint::Ppc))
            }
            IsaConstraint::Seg => {
                *self != IsaVersion::Xenon && *self != IsaVersion::Amazon
            }
            IsaConstraint::Ec | IsaConstraint::Tlb | IsaConstraint::Rfi => {
                *self != IsaVersion::Xenon &&
                    (*self == IsaVersion::RIOS || *self == IsaVersion::RIOS2 || self.supports(IsaConstraint::Ppc))
            }
            IsaConstraint::TlbSw => {
                // entries in the extended opcode table for TlbSw generally were `invalid!(Ppc)`,
                // reflecting that these instructions generally were removed by the time PowerPC
                // got to market.
                *self == IsaVersion::e500 || *self == IsaVersion::e500mc || *self == IsaVersion::A2
            }
            IsaConstraint::Embedded => {
                static ISA_EMBEDDED: &'static [IsaVersion] = &[
                    IsaVersion::V2_03, IsaVersion::V2_04,
                    IsaVersion::V2_05, IsaVersion::V2_06,
                    IsaVersion::A2,
                    IsaVersion::V2_07,
                ];
                ISA_EMBEDDED.contains(&self)
            }
            IsaConstraint::Ppc64 => {
                // it is presumably not true that all Power 2.02+ implementations support 64-bit
                // instructions (and the operating mode), but that is currently true of the
                // individual implementations mentioned in IsaVersion..
                //
                // Amazon is on this list as RS64 seems to have supported 64-bit from the get-go,
                // > The RS64 is also used in the AS/400 (called A35).
                *self == IsaVersion::Amazon ||
                *self == IsaVersion::Xenon || *self == IsaVersion::Cell ||
                    *self == IsaVersion::V2_0 || *self == IsaVersion::V2_01 ||
                    self.supports(IsaConstraint::PowerIsa202)
            }
            IsaConstraint::POWER => {
                // POWER1-specific quirks. this might mean slightly different instructions (`tlbi`
                // rather than `tlbie`), different operands (again, see `tlbi`), or instructions
                // that were deleted in the move to PowerPC. generally, POWER1 (and POWER2) are
                // constraints that should be used carefully, because "All" also supports
                // POWER1/POWER2 in support of decoding deleted instructions, but use of the ISA
                // constraint should not move decoding *away* from interpreting sequence in the
                // "latest" reasonable meaning.
                *self == IsaVersion::RIOS || *self == IsaVersion::RIOS2
            }
            IsaConstraint::POWER2 => {
                // "POWER2" is odd because it defines instructions that generally are not supported
                // *after* POWER2 (e.g. removed in PowerPC, etc)
                *self == IsaVersion::RIOS2
            }
            IsaConstraint::PowerIsa200 => {
                static ISA_GE_200: &'static [IsaVersion] = &[
                    IsaVersion::Amazon,
                    IsaVersion::Cell, IsaVersion::Xenon,
                    IsaVersion::V2_0_32b, IsaVersion::V2_01_32b,
                    IsaVersion::V2_0, IsaVersion::V2_01,
                    IsaVersion::V2_02,
                    IsaVersion::V2_03, IsaVersion::V2_04,
                    IsaVersion::V2_05, IsaVersion::V2_06,
                    IsaVersion::e500mc,
                    IsaVersion::A2,
                    IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1
                ];
                ISA_GE_200.contains(&self)
            }
            IsaConstraint::PowerIsa202 => {
                static ISA_GE_202: &'static [IsaVersion] = &[
                    // > The PPE is based on Version 2.02 of the PowerPC
                    // > Architecture, which offers many of the features required
                    // > for the application spaces targeted by the CBEA
                    IsaVersion::Cell,
                    IsaVersion::V2_02,
                    IsaVersion::V2_03, IsaVersion::V2_04,
                    IsaVersion::V2_05, IsaVersion::V2_06,
                    IsaVersion::e500mc,
                    IsaVersion::A2,
                    IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1
                ];
                ISA_GE_202.contains(&self)
            }
            IsaConstraint::PowerIsa203 => {
                static ISA_GE_203: &'static [IsaVersion] = &[
                    // seems that some instructions (lwsi, stswi, ..) are supported on Cell, so
                    // says RPCS3. that means Cell is 2.03+?
                    IsaVersion::Cell,
                    // notably, dcbtls and related decodes on e500
                    IsaVersion::e500,
                    IsaVersion::V2_03, IsaVersion::V2_04,
                    IsaVersion::V2_05, IsaVersion::V2_06,
                    IsaVersion::e500mc,
                    IsaVersion::A2,
                    IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1
                ];
                ISA_GE_203.contains(&self)
            }
            IsaConstraint::PowerIsa205 => {
                static ISA_GE_205: &'static [IsaVersion] = &[
                    IsaVersion::e500, IsaVersion::e500mc,
                    IsaVersion::A2,
                    IsaVersion::V2_05,
                    IsaVersion::V2_06, IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1,
                ];
                ISA_GE_205.contains(&self)
            }
            IsaConstraint::PowerIsa206 => {
                static ISA_GE_206: &'static [IsaVersion] = &[
                    IsaVersion::e500, IsaVersion::e500mc,
                    IsaVersion::V2_06, IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1,
                ];
                ISA_GE_206.contains(&self)
            }
            IsaConstraint::PowerIsa207 => {
                static ISA_GE_207: &'static [IsaVersion] = &[
                    IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1,
                ];
                ISA_GE_207.contains(&self)
            }
            IsaConstraint::PowerIsa30 => {
                static ISA_GE_30: &'static [IsaVersion] = &[
                    IsaVersion::V3_0, IsaVersion::V3_1,
                ];
                ISA_GE_30.contains(&self)
            }

            IsaConstraint::DFP => {
                static DFP_VERSIONS: &'static [IsaVersion] = &[
                    // v2.05 was standardized in 2007, well after Xenon and Cell, so they are
                    // conspicuously missing here!
                    IsaVersion::V2_05, IsaVersion::V2_06, IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1
                ];
                DFP_VERSIONS.contains(&self)
            }

            IsaConstraint::DFPQA | IsaConstraint::DFP25 => {
                static DFP25_VERSIONS: &'static [IsaVersion] = &[
                    IsaVersion::V2_05,
                    IsaVersion::V2_06, IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1
                ];
                DFP25_VERSIONS.contains(&self)
            }

            IsaConstraint::DFP26 => {
                static DFP26_VERSIONS: &'static [IsaVersion] = &[
                    IsaVersion::V2_06, IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1
                ];
                DFP26_VERSIONS.contains(&self)
            }

            IsaConstraint::DFP27 => {
                static DFP27_VERSIONS: &'static [IsaVersion] = &[
                    IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1
                ];
                DFP27_VERSIONS.contains(&self)
            }

            IsaConstraint::AltiVec_LE206 => {
                self.supports(IsaConstraint::AltiVec) && !self.supports(IsaConstraint::PowerIsa206)
            }

            IsaConstraint::AltiVec => {
                static ALTIVEC_VERSIONS: &'static [IsaVersion] = &[
                    IsaVersion::Xenon, IsaVersion::Cell,
                    /* V2.02 does not have AltiVec */
                    IsaVersion::V2_03, IsaVersion::V2_04,
                    IsaVersion::V2_05, IsaVersion::V2_06, IsaVersion::V2_07,
                    IsaVersion::V3_0, IsaVersion::V3_1
                ];
                ALTIVEC_VERSIONS.contains(&self)
            }

            IsaConstraint::AltiVec_NonPower => {
                static ALTIVEC_VERSIONS: &'static [IsaVersion] = &[
                    // HELP: does Cell support `dss`, `dssall`, etc?
                    IsaVersion::Xenon, IsaVersion::Cell,
                ];
                ALTIVEC_VERSIONS.contains(&self)
            }

            IsaConstraint::VMX128 => {
                *self == IsaVersion::Xenon
            }

            IsaConstraint::VSX => {
                *self == IsaVersion::V2_07 || *self == IsaVersion::V3_0 || *self == IsaVersion::V3_1
            }

            IsaConstraint::LMA => {
                panic!("unhandled constraint: {:?}", constraint);
            }
        }
    }
}

/// a decoded Power ISA instruction.
///
/// `Instruction` describes the "simplest" book-defined interpretation: no aliasing is applied,
/// `Opcode` maps to individual opcodes with headings in the Power ISA books.
///
/// see `compute_alias` for reinterpretation as book-defined assembler aliases. note that for
/// display purposes, the default behavior is already to display assembler aliases where defined.
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash)]
pub struct Instruction {
    opcode: Opcode,
    operands: [Option<Operand>; 5],
    // the state `Rc` on instructions..
    rc: bool,
    // the state of `AA` on instructions. only relevant for branches.
    aa: bool,
    // the state of `LK` on instructions. only relevant for branches(?)
    lk: bool,
    // the state of `OE` on instructions. only relevant for some arithmetic(?)
    oe: bool,
    // which form of hinting does the conditional branch in this instruction have?
    //
    // if this instruction is not branch-hinted, this is None.
    hint_style: Option<HintStyle>,
    len: u64,
}

/// this is only public to use in tests with `compute_branch_mnemonic`. don't use it.
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash)]
pub enum HintStyle {
    /// the BO field is interpreted as described in documents like:
    /// > PowerPC Microprocessor Family: The Programming Environments For 32-Bit Microprocessors
    ///
    /// which is to say, default prediction target depends on the opcode and offset sign, with a
    /// bit to optionally invert the prediction.
    Legacy,
    /// the BO field is interpreted as described in any of the Power ISA books since 2.00
    ///
    /// here, the default prediction behavior is hardware-defined, with taken and not-taken hints
    /// describe by the BO field.
    PowerIsa,
}

impl Instruction {
    fn init_from(alias: &InstructionAlias) -> Self {
        let this = Instruction {
            opcode: Opcode::XORI,
            operands: alias.operands.clone(),
            rc: alias.rc(),
            aa: alias.aa(),
            lk: alias.lk(),
            oe: alias.oe(),
            hint_style: alias.hint_style(),
            len: alias.len,
        };
        this
    }

    /// get the [`Opcode`] for this instruction.
    pub fn opcode(&self) -> Opcode {
        self.opcode
    }

    /// get the `idx`'th operand for this instruction.
    ///
    /// returns `None` if there is no operand at the requested index.
    pub fn operand(&self, idx: u8) -> Option<&Operand> {
        if let Some(op) = self.operands.get(idx as usize) {
            op.as_ref()
        } else {
            None
        }
    }

    /// get the number of operands for this instruction.
    ///
    /// `Instruction::operand` returns `Some` for any `idx` below the returned count, and `None`
    /// otherwise..
    pub fn operand_count(&self) -> usize {
        let mut count = 0;
        for op in self.operands.iter() {
            if op.is_some() {
                count += 1;
            } else {
                break;
            }
        }
        count
    }

    /// get the instruction's RECORD (`Rc`) bit.
    ///
    /// the RECORD bit indicates if the condition register should be updated as part of executing
    /// this instruction. it is indicated as a trailing `.` after instruction mnemonics in textual
    /// form.
    pub fn rc(&self) -> bool {
        self.rc
    }

    /// get the instruction's Absolute Address (`AA`) bit.
    ///
    /// the Absolute Address bit indicates if a branch uses a relative or absolute addressing mode.
    /// this is unlikely to be useful; it is redundant with both the `BranchAbs`/`BranchOffset`
    /// operand forms and `BA`/`BCA`/`BLA`/`BCLA` where `AA` already resulted in an opcode with
    /// trailing `A` meaning this same thing.
    ///
    /// for non-branches this is not meaningful and always `false`.
    pub fn aa(&self) -> bool {
        self.aa
    }

    /// get the instruction's LINK (`Lk`) bit.
    ///
    /// the LINK bit indicates if a branch sets the Link Register (`lr`) with the address of the
    /// instruction after the branch as part of execution. like `aa()` above, this is redundant
    /// with opcodes which include the "set link" implication: `BL`, `BCL`, `BLA`, `BCLA`.
    ///
    /// for non-branches this is not meaningful and always `false`.
    pub fn lk(&self) -> bool {
        self.lk
    }

    /// get the instruction's OE bit.
    ///
    /// the OE bit indicates if this instruction sets the OV and SO bits in XER as part of
    /// execution. this is also indicated with a trailing `o` after the instruction mnemonic but
    /// before an optional `.` in textual form.
    ///
    /// this is only relevant for XO-form instructions, mostly arithmetic.
    pub fn oe(&self) -> bool {
        self.oe
    }

    /// accumulate this instruction with a `DisplayRules` to get a tuple out which is suitable for
    /// `DisplaySink` or any general `format!()` use.
    #[cfg(feature = "fmt")]
    pub fn display_rules<'a, 'rules, Rules>(
        &'a self,
        rules: &'rules Rules,
    ) -> display::InstructionRuleBundle<'a, 'rules, Rules> {
        display::InstructionRuleBundle {
            instr: self,
            rules,
        }
    }

    /// reinterpret this instruction as a book-defined assembler alias, if one is defined.
    ///
    /// if no alias is defined for this instruction and operands, the returned `InstructionAlias`
    /// will instead be this instruction with an `AliasOp::Hardware` opcode.
    pub fn compute_alias(&self) -> InstructionAlias {
        <InstructionAlias as yaxpeax_arch::InstructionAlias<Self>>::compute_alias(self)
    }
}

impl LengthedInstruction for Instruction {
    type Unit = AddressDiff<<Power as Arch>::Address>;

    #[inline]
    fn len(&self) -> Self::Unit {
        AddressDiff::from_const(self.len)
    }

    #[inline]
    fn min_size() -> Self::Unit {
        // TODO: this is really a question of the ISA version being decoded, since VLE instructions
        // could be as small as two bytes, but everything else has a four-byte floor. not really
        // expressible in yaxpeax-arch terms..
        AddressDiff::from_const(4)
    }
}

impl Default for Instruction {
    /// the "default" instruction is `xori r0, r0, 0`.
    fn default() -> Self {
        Self {
            opcode: Opcode::XORI,
            operands: [
                // fill out the operands so this at least has the same shape as an equivalent
                // decoded instruction..
                Some(Operand::Register(Register::new(0))),
                Some(Operand::Register(Register::new(0))),
                Some(Operand::ImmU16(0)),
                None,
                None,
            ],
            rc: false,
            aa: false,
            lk: false,
            oe: false,
            hint_style: None,
            len: 4,
        }
    }
}

#[allow(non_camel_case_types)]
#[non_exhaustive]
#[allow(missing_docs)]
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash, PartialOrd, Ord)]
pub enum Opcode {
    TDI = 0,
    TD,
    TWI,
    TW,
    MULLD,
    /// "POWER mnemonic: muli"
    MULLI,
    MULLW,
    MULHWU,
    MULHW,
    MULHDU,
    MULHD,
    /// "POWER mnemonic: sfi"
    SUBFIC,
    SUBFZE,
    SUBFE,
    SUBFME,
    SUBFC,
    SUBF,
    CMPLI,
    CMPL,
    CMPI,
    CMP,
    ADD,
    ADDE,
    /// "POWER mnemonic: ai"
    ADDIC,
    ADDC,
    /// add immediate, as in `addi Rt, Ra, SI`.
    ///
    /// note that if `Ra` is 0 then the value 0 is used, not GPR 0.
    /// "POWER mnemonic: cal"
    ADDI,
    /// "POWER mnemonic: cau"
    ADDIS,
    ADDZE,
    ADDME,
    BC,
    BCA,
    BCL,
    BCLA,
    SC,
    /// the POWER1/POWER2 predecessor to "svc". this is only decoded when asking for one of those
    /// two processor types via `RIOS` or `RIOS2`.
    SVC,
    B,
    BA,
    BL,
    BLA,
    RLMI,
    RLDIMI,
    RLWIMI,
    RLWINM,
    RLWNM,
    OR,
    ORC,
    ORI,
    ORIS,
    XOR,
    XORI,
    XORIS,
    ANDI,
    ANDIS,
    AND,
    NAND,
    ANDC,
    LD,
    LDU,
    LWA,
    LWAX,
    LWAUX,
    LWZ,
    LWZU,
    LWZUX,
    LBZ,
    LBZX,
    LBZU,
    LBZUX,
    STD,
    STDU,
    STDX,
    STDUX,
    STDCX,
    STW,
    STWU,
    STWX,
    STWCX,
    STWUX,
    STB,
    STBU,
    STBX,
    STBUX,
    LHZ,
    LHZU,
    LHZX,
    LHZUX,
    LHA,
    LHAU,
    LHAX,
    LHAUX,
    LHBRX,
    LWBRX,
    LWARX,
    LWZX,
    STH,
    STHU,
    STHX,
    STHUX,
    LMW,
    STMW,
    LFS,
    LFSU,
    LFSX,
    LFSUX,
    LFD,
    LFDX,
    LFDU,
    LFDUX,

    LBDX,
    LHDX,
    LWDX,
    LDDX,
    LFDDX,

    LFDP,
    LFDPX,

    LFQ,
    STFS,
    STFSU,
    STFD,
    STFDU,
    STFQ,
    STFDP,
    STFQU,
    LSWI,
    LSWX,
    LSCBX,
    SLE,
    SLQ,

    NEG,
    MUL,
    NOR,
    ABS,
    NABS,

    DIV,
    DIVW,
    DIVWU,
    DIVS,
    DIVD,
    DIVDU,

    EXTSW,
    EXTSH,
    EXTSB,

    STFSX,
    STFSUX,
    STFDUX,

    STFDPX,

    STFDX,
    STFIWX,
    STFQUX,
    STFQX,
    STHBRX,
    STWBRX,
    STSWX,
    STSWI,

    LFQU, // POWER2 only?
    LFQX,
    LFQUX,

    TLBIA,
    TLBIE,
    /// the POWER/POWER2-only form of TLB invalidation
    TLBI,
    /// e500 and related software TLB management?
    TLBRE,
    TLBWE,
    TLBSX,
    TLBIVAX,

    SLIQ,
    SLEQ,
    SLBIA,
    SLBIE,
    SLBMTE,
    SLBMFEV,
    SLBMFEE,

    EQV,

    ECIWX,
    ECOWX,

    EIEIO,
    MBAR,

    SRW,
    SRD,
    SRE,
    SREA,
    SREQ,
    SRIQ,
    SRQ,
    SRLQ,
    SRAW,
    SRAWI,
    SRAD,
    SRADI,
    SRAIQ,
    SRLIQ,
    SRAQ,

    SLLQ,
    SLLIQ,

    DCBT,
    /// the specific form of `dcbt` as understood by POWER implementations after RIOS2 and before
    /// PowerPC and the ~v2.03 era of processors. practically this is probably only produced when
    /// decoding instructions as by `IsaVersion::Amazon`.
    ///
    /// primarily this form of `dcbt` has a narrower `TH` hint with different interpretations than
    /// later processors.
    DCBT_AS,
    DCBTLS,
    DCBI,
    DCLST,
    ICBI,

    CLI,
    CLF,
    CLCS,

    RAC,
    RRIB,
    DOZ,
    DOZI,

    TLBSYNC,
    SYNC,
    ISYNC,

    MXRCR,
    MCRXR,

    MFTB,
    MFCR,
    MFOCRF,
    MFMSR,
    MFSR,
    MFSRI,
    MFSRIN,
    MFSPR,
    MCRF,
    MCRFS,
    MTOCRF,
    MTCRF,
    MTSR,
    MTSRD,
    MTSPR,
    MTMSR,
    MTMSRD,
    /// the specific form of `mtmsrd` understood by Xenon, where L=1 changes this instruction to
    /// the unique-to-Xenon `mtmsree`.
    MTMSRD_Xenon,
    MTSRIN,
    MTSRDIN,
    MFFS,
    MCFRS,
    MTFSFI,
    MTFSF,
    MTFSB0,
    MTFSB1,

    LDX,
    LDUX,
    LDARX,
    SLW,
    SLD,
    CNTLZW,
    CNTLZD,

    CRXOR,
    CROR,
    CRNOR,
    CRAND,
    CRNAND,
    CRANDC,
    CRORC,
    CREQV,

    BCCTR,
    BCLR,

    DCBA,
    DCBST,
    DCBTST,
    DCBF,
    DCBZ,
    /// an alternate form of `dcbz` which only exists on Xenon.
    ///
    /// `dcbz` has a bit field which is ignored in decoding in most Power implementations, but
    /// Xenia requires it to be 0 (producing `dcbz`) or 1 (producing `dcbz128`). i do not know if
    /// this impliex Xenon rejects other forms of dcbz, or if Xenia overly strict.
    DCBZ128,
    MASKIR,
    MASKG,

    /// these `Data Stream ...` instructions are defined by AltiVec but `ALTIVECPOWERISAPEM.pdf`
    /// states they are not present in AltiVec as incorporated into the Power ISA (that would be
    /// .. v2.01 or so?).
    ///
    /// it is not clear to me what implementations *do* have these instructions, but at the bare
    /// minimum these are known to exist in the Cell PPU.
    DST,
    DSTT,
    DSS,
    DSSALL,
    DSTST,
    DSTSTT,

    RLDCL,
    RLDIC,
    RLDICL,
    RLDCR,
    RLDICR,

    RFI,
    RFID,
    RFSVC,
    HRFID,

    BBELR,
    BBLELS,

    ATTN,
    MSGCLR,
    MSGSND,
    MSGCLRP,
    MSGSNDP,

    // float/double
    DRSP,
    DSUB,
    DADD,
    DADDQ,
    DMUL,
    DMULQ,
    DDIV,

    FMR,
    FABS,
    FNABS,
    FNEG,
    FRE,
    FRES,
    FRSP,
    FMUL,
    FMULS,
    FDIV,
    FDIVS,
    FSUB,
    FSUBS,
    FADD,
    FADDS,
    FSQRT,
    FSQRTS,
    FSEL,
    ISEL,
    FRIN,
    FRIM,
    FRIP,
    FRIZ,
    FRSQRTE,
    FRSQRTES,
    FLSQRT,
    FMSUB,
    FMSUBS,
    FMADD,
    FMADDS,
    FNMSUB,
    FNMSUBS,
    FNMADD,
    FNMADDS,

    FTDIV,
    FTSQRT,
    FCMPO,
    FCMPU,
    FCPSGN,

    DQUA,
    DQUAQ,
    DQUAI,
    DQUAIQ,
    DSCLI,
    DSCLIQ,
    DSCRI,
    DSCRIQ,
    DRDPQ,
    DRRND,
    DRRNDQ,
    DSUBQ,
    DDIVQ,
    DIEX,
    DIEXQ,
    DXEX,
    DXEXQ,
    DCMPO,
    DCMPU,
    DCMPOQ,
    DCMPUQ,
    DCFFIX,
    DCTFIX,
    DCFFIXQ,
    DCTFIXQ,
    DCTDP,
    DCTQPQ,
    DRINTN,
    DRINTNQ,
    DRINTX,
    DRINTXQ,
    DTSTDC,
    DTSTDCQ,
    DTSTDG,
    DTSTDGQ,
    DTSTSF,
    DTSTSFQ,
    DTSTEX,
    DTSTEXQ,
    DENBCD,
    DENBCDQ,
    DDEDPD,
    DDEDPDQ,

    FCFIDU,
    FCFIDUS,
    FCFIDS,
    FCTIW,
    FCTIWZ,
    FCTIWU,
    FCTIWUZ,
    FCTIDU,
    FCTIDUZ,
    FCFID,
    FCTID,
    FCTIDZ,

    // all vector ops
    VMHADDSHS,
    VMHRADDSHS,
    VMLADDUHM,
    VMSUMUBM,
    VMSUMMBM,
    VMSUMUHM,
    VMSUMUHS,
    VMSUMSHM,
    VMSUMSHS,
    VSEL,
    VPERM,
    VSLDOI,
    VMADDFP,
    VNMSUBFP,

    // mixed vector/lma
    VADDUBM,
    VMAXUB,
    VRLB,
    VCMPEQUB,
    VMULOUB,
    VADDFP,
    VMRGHB,
    VPKUHUM,
    MULHHWU,
    MACHHWU,
    VADDUHM,
    VMAXUH,
    VRLH,
    VMULOUH,
    VSUBFP,
    VMRGHH,
    VPKUWUM,
    MULHHWW,
    NMACHHW,
    VADDUWM,
    VMAXUW,
    VRLW,
    VMRGHW,
    VPKUHUS,
    VPKUWUS,
    MACHHWS,
    VMAXSB,
    VSLB,
    VMULOSB,
    VREFP,
    VMRGLB,
    VPKSHUS,
    MULCHWU,
    MACCHWU,
    VMAXSH,
    VSLH,
    VMULOSH,
    VRSQRTEFP,
    VMRGLH,
    VPKSWUS,
    MULCHW,
    NMACCHW,
    VADDCUW,
    VMAXSW,
    VSLW,
    VEXPTEFP,
    VMRGLW,
    VPKSHSS,
    VPKSWSS,
    VSL,
    VLOGEFP,
    MACCHWS,
    VADDUBS,
    VMINUB,
    VSRB,
    VMULEUB,
    VRFIN,
    VSPLTB,
    VUPKHSB,
    VADDUHS,
    VMINUH,
    VSRH,
    VMULEUH,
    VRFIZ,
    VSPLTH,
    VUPKHSH,
    VADDUWS,
    VMINUW,
    VSRW,
    VRFIP,
    VSPLTW,
    VUPKLSB,
    VSR,
    VRFIM,
    VUPKLSH,
    VADDSBS,
    VMINSB,
    VSRAB,
    VMULESB,
    VCFUX,
    VSPLTISB,
    VPKPX,
    MULLHWU,
    MACLHWU,
    VADDSHS,
    VMINSH,
    VSRAH,
    VMULESH,
    VCFSX,
    VSPLTISH,
    VUPKHPX,
    MULLHW,
    NMACLHW,
    VADDSWS,
    VMINSW,
    VSRAW,
    VCTUXS,
    VSPLTISW,
    VCTSXS,
    VUPKLPX,
    MACLHWS,
    VSUBUBM,
    VAVGUH,
    VAND,
    VMAXFP,
    VSLO,
    VSUBUHM,
    VAVGUW,
    VANDC,
    VCMPEQUH,
    VMINFP,
    VSRO,
    VAVGSH,
    MACHHW,
    VSUBUWM,
    VAVGUB,
    VOR,
    VCMPEQUW,
    VXOR,
    VCMPEQFP,
    VAVGSB,
    VNOR,
    MACCHW,
    VSUBCUW,
    VAVGSW,
    VSUM4UBS,
    VSUM4SHS,
    VSUM2SWS,
    VSUM4SBS,
    MACLHW,
    VCMPGEFP,
    VSUBUBS,
    MFVSCR,
    VCMPGTUB,
    VCMP4UBS,
    VSUBUHS,
    MTVSCR,
    VCMPGTUH,
    VSUBUWS,
    VCMPGTUW,
    VCMPGTFP,
    VSUBSBS,
    VCMPGTSB,
    VSUBSHS,
    VCMPGTSH,
    VSUBSWS,
    VCMPGTSW,
    VSUMSWS,
    VCMPBFP,

    /// VMX128 instructions
    VUPKHSB128,
    VUPKLSB128,
    VCMPEQFP128,
    VCMPGEFP128,
    VCMPGTFP128,
    VCMPBFP128,
    VCMPEQUW128,
    VMAXFP128,
    VMINFP128,
    VMRGHW128,
    VMRGLW128,

    LVSL128,
    LVSR128,
    LVEWX128,
    LVX128,
    STVX128,
    LVXL128,
    STVEWX128,
    STVXL128,
    LVLX128,
    LVRX128,
    STVLX128,
    STVRX128,
    LVLXL128,
    LVRXL128,
    STVLXL128,
    STVRXL128,
    VSLDOI128,

    VPERM128,
    VPKSHSS128,
    VPKSHUS128,
    VPKSWSS128,
    VPKSWUS128,
    VPKUHUM128,
    VPKUHUS128,
    VPKUWUM128,
    VPKUWUS128,
    VADDFP128,
    VSUBFP128,
    VMULFP128,
    VMADDFP128,
    VMADDCFP128,
    VNMSUBFP128,
    VMSUM3FP128,
    VMSUM4FP128,
    VAND128,
    VANDC128,
    VNOR128,
    VOR128,
    VXOR128,
    VSEL128,
    VSLO128,
    VSRO128,

    VSRAW128,
    VRLW128,
    VSLW128,
    VSRW128,

    VPERMWI128,
    VCFPSXWS128,
    VCFPUXWS128,
    VCSXWFP128,
    VCUXWFP128,
    VRFIM128,
    VRFIN128,
    VRFIP128,
    VRFIZ128,
    VPKD3D128,
    VREFP128,
    VRSQRTEFP128,
    VEXPTEFP128,
    VLOGEFP128,
    VRLIMI128,
    VSPLTW128,
    VSPLTISW128,
    VUPKD3D128,

    // first added in one of the Blue Gene CPUs, since standardized in at least 2.07
    WRTEE,
    WRTEEI,

    // AltiVec
    LVSL,
    LVSR,
    STVEPX,
    STVEPXL,
    // lvlx and lvrx are strange in that the AltiVec manual does not mention them, Power v2.03 UISA
    // mentions them only in Table 8, but does not define them, and Xenia decodes them either way.
    //
    // TODO: assuming these were underdocumented and in all AltiVec with the rest of the baseline
    // vector instructions until i learn otherwise..
    LVLX,
    LVRX,
    LVX,
    LVXL,
    LVEBX,
    LVEHX,
    LVEWX,
    STVX,
    STVXL,
    STVLX,
    STVRX,
    STVLXL,
    STVRXL,
    STVEBX,
    STVEHX,
    STVEWX,

    // this appears to be undocumented and only present in Xenon and Cell?
    LVLXL,
    LVRXL,

    // "Category: 64-bit"
    LDBRX,
    STDBRX,

    // transactional instructions on v2.07+
    TABORT,
    TABORTDC,
    TABORTDCI,
    TABORTWC,
    TABORTWCI,
    TBEGIN,
    TEND,
    TCHECK,
    TSR,
    TRECLAIM,
    TRECHKPT,

    /// the various Gekko paired singles instructions
    DCBZ_L,

    PS_SUM0,
    PS_SUM1,
    PS_MULS0,
    PS_MULS1,
    PS_MADDS0,
    PS_MADDS1,
    PS_DIV,
    PS_SUB,
    PS_ADD,
    PS_SEL,
    PS_RES,
    PS_MUL,
    PS_RSQRTE,
    PS_MSUB,
    PS_MADD,
    PS_NMSUB,
    PS_NMADD,

    PS_NEG,
    PS_MR,
    PS_NABS,
    PS_ABS,

    PS_CMPU0,
    PS_CMPO0,
    PS_CMPU1,
    PS_CMPO1,

    PS_MERGE00,
    PS_MERGE01,
    PS_MERGE10,
    PS_MERGE11,

    PSQ_L,
    PSQ_LU,
    PSQ_LX,
    PSQ_LUX,
    PSQ_ST,
    PSQ_STU,
    PSQ_STX,
    PSQ_STUX = 697,
    // v--------^
    // don't forget to keep this up to date with the array in display.rs!
}

impl Opcode {
    /// get the opcode as a lowercase string.
    #[cfg(feature = "fmt")]
    pub fn name(&self) -> &'static str {
        let id = *self as u16;
        display::OPCODES[id as usize]
    }

    /// return `true` if this instruction is one of the various forms of branch opcode.
    pub fn is_branch(&self) -> bool {
        match self {
            Opcode::B | Opcode::BL | Opcode::BA | Opcode::BLA |
            Opcode::BC | Opcode::BCL | Opcode::BCA | Opcode::BCLA |
            Opcode::BCLR |
            Opcode::BCCTR => true,
            _ => false
        }
    }
}

/// the controls for how `sync` .. syncs.
///
/// described in Book II, `Synchronize X-form` under `Memory Barrier Instructions`.
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash, PartialOrd, Ord)]
pub enum SyncControl {
    /// "heavyweight sync". the resulting sync instruction is `sync`.
    ///
    /// > The memory barrier provides an ordering function for the storage accesses associated with
    /// > all instructions that are executed by the processor executing the sync instruction. The
    /// > applicable pairs are all pairs ai ,bj in which bj is a data access, except that if ai is
    /// > the storage access caused by an icbi instruction then bj may be performed with respect to
    /// > the processor executing the sync instruction before ai is performed with respect to that
    /// > processor.
    Default = 0,
    /// "lightweight sync". the resulting sync instruction is `lwsync`.
    ///
    /// > The memory barrier provides an ordering function for the storage accesses caused by Load,
    /// > Store, and dcbz instructions that are executed by the processor executing the sync
    /// > instruction and for which the specified storage location is in storage that is Memory
    /// > Coherence Required and is neither Write Through Required nor Caching Inhibited. The
    /// > applicable pairs are all pairs ai ,bj of such accesses except those in which ai is an
    /// > access caused by a Store or dcbz instruction and bj is an access caused by a Load
    /// > instruction.
    LW = 1,
    /// the resulting instruction is `ptesync`.
    ///
    /// > The set of storage accesses that is ordered by the memory barrier is described in the
    /// > section entitled “Synchronize Instruction” in Book III, as are additional properties of
    /// > the sync instruction with L=2.
    PTE = 2,
    /// > The value L = 3 is reserved, and the results of executing a sync instruction with L=3 are
    /// > boundedly undefined.
    Reserved = 3,
}

impl SyncControl {
    #[inline(always)]
    fn from_bits(b: u8) -> Self {
        match b {
            0 => SyncControl::Default,
            1 => SyncControl::LW,
            2 => SyncControl::PTE,
            _ => SyncControl::Reserved,
        }
    }
}

/// a Power ISA GPR, with number in the range 0..31 (inclusive).
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash, PartialOrd, Ord)]
pub struct Register {
    reg: u8,
}

impl Register {
    /// create a struct describing `r<N>`.
    ///
    /// panics if `reg` is not a valid register number (e.g. is greater than 31)
    pub fn new(reg: u8) -> Self {
        assert!(reg < 32);

        Self { reg }
    }

    /// get the register number for this General Purpose Register.
    pub fn num(&self) -> u8 {
        self.reg
    }
}

/// a Power ISA FPR, with number in the range 0..31 (inclusive).
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash, PartialOrd, Ord)]
pub struct FPR {
    reg: u8,
}

impl FPR {
    /// create a struct describing `fr<N>`.
    ///
    /// panics if `reg` is not a valid register number (e.g. is greater than 31)
    pub fn new(reg: u8) -> Self {
        assert!(reg < 32);

        Self { reg }
    }

    /// get the register number for this Floating Point Register.
    pub fn num(&self) -> u8 {
        self.reg
    }
}

// from `Move To Special Purpose Register XFX-form`:
// 1 => XER
// 8 => LR
// 9 => CTR
/// a Power ISA SPR.
///
/// the specific numbers and interpretations vary across processors. help is welcome: i'd love
/// references to include, and possibly SPR tables in the library!
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash, PartialOrd, Ord)]
pub struct SPR {
    reg: u16,
}

impl SPR {
    /// create a new SPR for a given register number.
    ///
    /// because SPR register numbers are not generally portable, this may or may not be reasonable
    /// to a given Power implementation.
    pub fn new(reg: u16) -> Self {
        Self { reg }
    }

    /// get the register number for this Special-Purpose Register.
    pub fn num(&self) -> u16 {
        self.reg
    }
}

/// a Power ISA vector register, with number in the range 0..31 (inclusive).
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash, PartialOrd, Ord)]
pub struct VR {
    reg: u8,
}

impl VR {
    /// create a struct describing `vr<N>`.
    ///
    /// panics if `reg` is not a valid register number (e.g. is greater than 31)
    pub fn new(reg: u8) -> Self {
        assert!(reg < 32);

        Self { reg }
    }

    /// get the register number for this vector register.
    pub fn num(&self) -> u8 {
        self.reg
    }
}

/// a vector register used in the Xenon VMX128 instructions. unlike `VR` with a standard 32
/// vector register file, `VR128` describes the extended Xenon 128 vector register file.
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash, PartialOrd, Ord)]
pub struct VR128 {
    reg: u8,
}

impl VR128 {
    /// create a struct describing higher-number `vr<N>` from VMX128.
    ///
    /// panics if `reg` is not a valid register number (e.g. is greater than 127)
    pub fn new(reg: u8) -> Self {
        assert!(reg < 128);

        Self { reg }
    }

    /// get the register number for this VMX128 register.
    ///
    /// this register form is only present in VMX128-only instructions. Xenon,
    /// the only ISA with the VMX128 extension, results in `VR` operands for
    /// typical AltiVec instructions, and `VR128` operands for the
    /// VMX128-specific additions.
    pub fn num(&self) -> u8 {
        self.reg
    }
}

/// the Gekko-specific Graphics Quantization Registers involved in paired-singles load/store
/// operations.
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash, PartialOrd, Ord)]
pub struct GQR {
    reg: u8,
}

impl GQR {
    /// create a struct describing `qr<N>`.
    ///
    /// panics if `reg` is not a valid register number (e.g. is greater than 7)
    pub fn new(reg: u8) -> Self {
        assert!(reg < 8);

        Self { reg }
    }

    /// get the register number for this Graphics Quantization Register.
    pub fn num(&self) -> u8 {
        self.reg
    }
}

#[non_exhaustive]
#[allow(missing_docs)]
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash)]
pub enum Operand {
    /// the control field for the behavior of a `sync` instruction.
    LL(SyncControl),

    /// a register in a Power ISA processor.
    Register(Register),

    /// a register in a Power ISA processor, or the value "0" if selecting r0.
    RegisterOrZero(Register),

    /// a memory access at `base` offset by `disp`.
    ///
    /// if `base` is `r0`, then the index is the address formed by sign-extending `disp` to address
    /// width.
    ///
    /// this is not descriptive of all POWER memory accesses; other accesses may be a pair of
    /// Register/RegisterOrZero
    MemoryDisp { base: Register, disp: i16 },

    /// typically a memory address at `base + index`.
    ///
    /// if `base` is `r0`, then the index is the literal value `0` rather than the value in `r0`.
    /// some instructions compute addresses with this operand rather than access memory, so the
    /// operand alone does not determine if an instruction does or does not perform a load/store.
    MemoryIndexed { base: Register, index: Register },

    /// a floating-point register in a Power ISA processor.
    FPR(FPR),

    /// a special-purpose register in a Power ISA processor.
    SPR(SPR),

    /// a vector register (either from `AltiVec` or later Power ISA versions which incorporate it)
    VR(VR),

    /// a vector register used in VMX128 instructions (as wide as [`VR`], but 128 of these rather than 32.)
    VR128(VR128),

    /// a graphics quantization register in a Gekko or Broadway processor.
    GQR(GQR),

    /// an immediate, sign-extended to the size of a GPR.
    ImmExts16(i16),

    /// an immediate 16-bit value, zero-extended to the size of a GPR.
    ImmU16(u16),

    /// an immediate 32-bit value.
    ImmU32(u32),

    /// the absolute address of a branch target, sign-extended to the size of PC.
    ///
    /// note that PC may be 32 bits in some implementations, or 64 bits in others.
    BranchAbs(i32),

    /// a relative branch offset, sign-extended to the size of PC.
    ///
    /// note that PC may be 32 bits in some implementations, or 64 bits in others.
    BranchOffset(i32),

    /// an immediate 16-bit value, sign-extended as a relative branch offset.
    ///
    /// this 16-bit value may be furhter sign-extended to 32 bits and handled in the same manner as
    /// `BranchOffset`, above.
    BranchOffset16(i16),

    /// an immediate 8-bit value.
    ///
    /// this is probably some kind of configuration value for the operation of an instruction,
    /// rather than a literal used as-encoded.
    Imm8(u8),

    /// a field in the `CR` special-purpose register.
    ///
    /// this references any of the 8 four-bit fields in the condition register.
    CrField(u8),

    /// a mask of fields in the Condition Register which are operated on.
    ///
    /// this is only produced as an operand in `mfocrf` or `mtocrf`. it can be converted to an
    /// equivalent `CrField`, but is a distinct type as those instructions have this operand
    /// assembled from and disassembled to a plain integer.
    CrMask(u8),

    /// a field in the `FPSCR` (Floating-Point Status and Control Register) special-purpose
    /// register.
    ///
    /// the Power ISA FPU has a distinct status and control register, `fpscr`, distinct from the
    /// scalar condition register `cr`. some instructions address individual `fpscr` fields with
    /// this operand type.
    FpscrField(u8),

    /// a single bit in the `CR` special-purpose register.
    ///
    /// this is one bit in an enclosing "CR field".
    CrBit(u8),

    /// a D3D pixel format selected as part of a VMX128 pixel pack/unpack operation.
    PixelFormat(PixelFormat),
}

/// one of the eight possible pixel formats that can be an indicated in a VMX128 d3d operation.
#[allow(missing_docs)] // HELP: if you know what these mean, fill in docs here! jeez..
#[derive(Debug, PartialEq, Eq, Copy, Clone, Hash, PartialOrd, Ord)]
pub enum PixelFormat {
    D3dColor = 0,
    NormShort2 = 1,
    NormPacked32 = 2,
    Float16_2 = 3,
    NormShort4 = 4,
    Float16_4 = 5,
    NormPacked64 = 6,
    /// the pixel format specified by the immediate encoding `0b111` is unknown to me!
    Format7 = 7,
}

impl PixelFormat {
    fn from_u8(u: u8) -> Self {
        static FORMATS: &'static [PixelFormat; 8] = &[
            PixelFormat::D3dColor, PixelFormat::NormShort2,
            PixelFormat::NormPacked32, PixelFormat::Float16_2,
            PixelFormat::NormShort4, PixelFormat::Float16_4,
            PixelFormat::NormPacked64, PixelFormat::Format7,
        ];
        FORMATS[u as usize]
    }
}

#[allow(missing_docs)]
impl Operand {
    /// reinterpret this operand as a [`SyncControl`].
    ///
    /// this will only not panic if the corresponding instruction is [`Opcode::SYNC`] (more
    /// precisely: this will panic iff the operand is not `Operand::LL`. `Operand::LL` is only
    /// produced if the opcode is `sync`.)
    pub fn as_ll(&self) -> Option<SyncControl> {
        let Operand::LL(ctrl) = self else {
            return None;
        };

        Some(*ctrl)
    }

    pub fn as_ll_unwrap(&self) -> SyncControl {
        self.as_ll().unwrap()
    }

    /// reinterpret this operand as a general-purpose register, `Register`.
    pub fn as_reg(&self) -> Option<Register> {
        let Operand::Register(reg) = self else {
            return None;
        };

        Some(*reg)
    }

    pub fn as_reg_unwrap(&self) -> Register {
        self.as_reg().unwrap()
    }

    /// reinterpret this operand as a `Register`, with the additional meaning that this operand has
    /// a value of 0 if the `Register` would be `r0`.
    ///
    /// generally, this operand is an index or offset, where "0" is intended to mean "this operand
    /// does not contribute to an effective address calculation".
    pub fn as_reg_or_zero(&self) -> Option<Register> {
        let Operand::RegisterOrZero(reg) = self else {
            return None;
        };

        Some(*reg)
    }

    pub fn as_reg_or_zero_unwrap(&self) -> Register {
        self.as_reg_or_zero().unwrap()
    }

    /// reinterpret this operand as a memory access to the given register and offset.
    ///
    /// this does not describe all memory operands, but `MemoryDisp` and `MemoryIndexed` together
    /// cover most.
    pub fn as_mem_disp(&self) -> Option<(Register, i16)> {
        let Operand::MemoryDisp { base, disp } = self else {
            return None;
        };

        Some((*base, *disp))
    }

    pub fn as_mem_disp_unwrap(&self) -> (Register, i16) {
        self.as_mem_disp().unwrap()
    }

    /// reinterpret this operand as an indexed access (probably) to `base + reg`.
    ///
    /// this does not describe all memory operands; register-indexed memory accesses in particular
    /// are not reflected here.
    pub fn as_mem_indexed(&self) -> Option<(Register, Register)> {
        let Operand::MemoryIndexed { base, index } = self else {
            return None;
        };

        Some((*base, *index))
    }

    pub fn as_mem_indexed_unwrap(&self) -> (Register, Register) {
        self.as_mem_indexed().unwrap()
    }

    /// reinterpret this operand as a floating-point register.
    pub fn as_fpr(&self) -> Option<FPR> {
        let Operand::FPR(fpr) = self else {
            return None;
        };

        Some(*fpr)
    }

    pub fn as_fpr_unwrap(&self) -> FPR {
        self.as_fpr().unwrap()
    }

    /// reinterpret this operand as a special-purpose register.
    ///
    /// there are some common special-purpose registers across POWER implementations, but
    /// ultimately the specifics of what special-purpose register numbers refer to is a
    /// per-processor question.
    pub fn as_spr(&self) -> Option<SPR> {
        let Operand::SPR(spr) = self else {
            return None;
        };

        Some(*spr)
    }

    pub fn as_spr_unwrap(&self) -> SPR {
        self.as_spr().unwrap()
    }

    /// reinterpret this operand as a vector register as used in VMX instructions.
    pub fn as_vr(&self) -> Option<VR> {
        let Operand::VR(vr) = self else {
            return None;
        };

        Some(*vr)
    }

    pub fn as_vr_unwrap(&self) -> VR {
        self.as_vr().unwrap()
    }

    /// reinterpret this operand as a vector register in a VMX128 instruction, addressing the wider
    /// 128-wide vector register file.
    pub fn as_vr128(&self) -> Option<VR128> {
        let Operand::VR128(vr) = self else {
            return None;
        };

        Some(*vr)
    }

    pub fn as_vr128_unwrap(&self) -> VR128 {
        self.as_vr128().unwrap()
    }

    /// reinterpret this operand as a Gekko/Broadway Graphics Quantization Register, used in some
    /// paired-single load/store operations.
    pub fn as_gqr(&self) -> Option<GQR> {
        let Operand::GQR(gqr) = self else {
            return None;
        };

        Some(*gqr)
    }

    pub fn as_gqr_unwrap(&self) -> GQR {
        self.as_gqr().unwrap()
    }

    /// reinterpret this operand as a bitmask describing CR fields.
    ///
    /// this operand is only used in `mtocrf` and `mfocrf`, where the "o" means "one", meaning the
    /// returned bitmask has only one bit set reflecting one field in the condition register.
    pub fn as_cr_mask(&self) -> Option<u8> {
        let Operand::CrMask(cr) = self else {
            return None;
        };

        Some(*cr)
    }

    pub fn as_cr_mask_unwrap(&self) -> u8 {
        self.as_cr_mask().unwrap()
    }

    /// reinterpret this operand as a CR field.
    ///
    /// the referenced condition register field indicates any of cr0 through to cr7.
    pub fn as_cr_field(&self) -> Option<u8> {
        let Operand::CrField(cr) = self else {
            return None;
        };

        Some(*cr)
    }

    pub fn as_cr_field_unwrap(&self) -> u8 {
        self.as_cr_field().unwrap()
    }

    /// reinterpret this operand as a single bit in a CR field.
    ///
    /// the bit is relative to the start of the condition register, which indicates both which of
    /// the eight CR fields and which of the four bits is referenced in the selected CR field.
    pub fn as_cr_bit(&self) -> Option<u8> {
        let Operand::CrBit(i) = self else {
            return None;
        };

        Some(*i)
    }

    pub fn as_cr_bit_unwrap(&self) -> u8 {
        self.as_cr_bit().unwrap()
    }

    /// reinterpret this operand as an FPSCR field.
    pub fn as_fpscr_field(&self) -> Option<u8> {
        let Operand::FpscrField(cr) = self else {
            return None;
        };

        Some(*cr)
    }

    pub fn as_fpscr_field_unwrap(&self) -> u8 {
        self.as_fpscr_field().unwrap()
    }

    /// reinterpret this operand as a Xenon D3D instruction pixel format.
    pub fn as_pixel_format(&self) -> Option<PixelFormat> {
        let Operand::PixelFormat(pf) = self else {
            return None;
        };

        Some(*pf)
    }

    pub fn as_pixel_format_unwrap(&self) -> PixelFormat {
        self.as_pixel_format().unwrap()
    }

    /// reinterpret this operand as an absolute branch destination.
    ///
    /// see the documentation on `Operand::BranchAbs` for advice on how to interpret this operand.
    pub fn as_branch_absolute(&self) -> Option<i32> {
        let Operand::BranchAbs(dest) = self else {
            return None;
        };

        Some(*dest)
    }

    pub fn as_branch_absolute_unwrap(&self) -> i32 {
        self.as_branch_absolute().unwrap()
    }

    /// reinterpret this operand as a branch offset.
    ///
    /// see the documentation on `Operand::BranchOffset` for advice on how to interpret this operand.
    pub fn as_branch_offset(&self) -> Option<i32> {
        let Operand::BranchOffset(offs) = self else {
            return None;
        };

        Some(*offs)
    }

    pub fn as_branch_offset_unwrap(&self) -> i32 {
        self.as_branch_offset().unwrap()
    }

    /// reinterpret this operand as a 16-bit branch offset.
    ///
    /// see the documentation on `Operand::BranchOffset16` for advice on how to interpret this operand.
    pub fn as_branch_offset16(&self) -> Option<i16> {
        let Operand::BranchOffset16(offs) = self else {
            return None;
        };

        Some(*offs)
    }

    pub fn as_branch_offset16_unwrap(&self) -> i16 {
        self.as_branch_offset16().unwrap()
    }

    /// reinterpret this operand as a 32-bit unsigned immediate.
    pub fn as_imm32(&self) -> Option<u32> {
        let Operand::ImmU32(i) = self else {
            return None;
        };

        Some(*i)
    }

    pub fn as_imm32_unwrap(&self) -> u32 {
        self.as_imm32().unwrap()
    }

    /// reinterpret this operand as a 16-bit signed immediate.
    ///
    /// if the underlying value was smaller (such as the 5-bit immediate in many instructions), it
    /// was sign-extended up to 16 bits as part of decoding.
    pub fn as_signed_imm(&self) -> Option<i16> {
        let Operand::ImmExts16(i) = self else {
            return None;
        };

        Some(*i)
    }

    pub fn as_signed_imm_unwrap(&self) -> i16 {
        self.as_signed_imm().unwrap()
    }

    /// reinterpret this operand as a 16-bit unsigned immediate.
    pub fn as_imm16(&self) -> Option<u16> {
        let Operand::ImmU16(i) = self else {
            return None;
        };

        Some(*i)
    }

    pub fn as_imm16_unwrap(&self) -> u16 {
        self.as_imm16().unwrap()
    }

    /// reinterpret this operand as an 8-bit unsigned immediate.
    pub fn as_imm8(&self) -> Option<u8> {
        let Operand::Imm8(i) = self else {
            return None;
        };

        Some(*i)
    }

    pub fn as_imm8_unwrap(&self) -> u8 {
        self.as_imm8().unwrap()
    }
}

#[allow(non_camel_case_types)]
#[derive(Copy, Clone, PartialEq, Eq, Debug)]
enum Format {
    // FP Single/Double
    A,
    D,
    Ddot,
    // an invented alternate to `D` for D-form instructions that access memory.
    Dmem,
    DS,
    // Embedded? but in 2.07 with VSE and all..
    E,
    I,
    M,
    MD,
    MDS,
    B,
    SC,
    VX,
    VC,
    VCdot,
    X,
    XS,
    XL,
    XFL,
    XO,
    XFX,
    Z22,
    Z23,
    PS_LST,
}

#[derive(Copy, Clone, PartialEq, Eq)]
enum PrimaryLookup {
    Illegal,
    // parts of decode space reserved for implementations. this complicates "all" architecture
    // decoding..
    ImplementationDefined,
    Undefined,
    Opc(Opcode, Format),
    Extension(&'static ExtensionTable),
    // handling major opcode 4 is not amenable to table lookup. the arm for this is more or less
    // open-coded with some tables involved. in particular, it is either the opcode for SPE (signal
    // processing extensions) or AltiVec/VMX/VSX vector extensions.
    Opc4,
    // opcodes 5 and 6 are used in VMX128, but not others.
    Opc5,
    Opc6,
    // these opcodes mostly are Gekko-only, but 0x38 overlaps with LFQ, present on other processors.
    Opc38,
    Opc39,
    Opc3C,
    Opc3D,
}

impl fmt::Debug for PrimaryLookup {
    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
        match self {
            PrimaryLookup::Illegal => {
                f.write_str("illegal opcode")
            }
            PrimaryLookup::ImplementationDefined => {
                f.write_str("implementation defined")
            },
            PrimaryLookup::Undefined => {
                f.write_str("undefined")
            },
            PrimaryLookup::Opc(opc, fmt) => {
                write!(f, "opcode={:?}, format={:?}", opc, fmt)
            },
            PrimaryLookup::Extension(_table) => {
                f.write_str("extension opcode")
            },
            PrimaryLookup::Opc4 => {
                f.write_str("opcode 4 extension space")
            },
            PrimaryLookup::Opc5 => {
                f.write_str("opcode 5 extension space (vmx128)")
            },
            PrimaryLookup::Opc6 => {
                f.write_str("opcode 6 extension space (vmx128)")
            },
            PrimaryLookup::Opc38 => {
                f.write_str("opcode 0x38")
            },
            PrimaryLookup::Opc39 => {
                f.write_str("opcode 0x39")
            },
            PrimaryLookup::Opc3C => {
                f.write_str("opcode 0x3c")
            },
            PrimaryLookup::Opc3D => {
                f.write_str("opcode 0x3d")
            },
        }
    }
}

#[derive(Copy, Clone, PartialEq, Eq, Debug)]
struct OpcodeRecord {
    lookup: PrimaryLookup,
    isa_constraint: IsaConstraint,
    category: Category,
}

macro_rules! invalid {
    () => {
        Some(OpcodeRecord {
            lookup: PrimaryLookup::Illegal,
            isa_constraint: IsaConstraint::All,
            category: Category::B,
        })
    };
    ($const:ident) => {
        Some(OpcodeRecord {
            lookup: PrimaryLookup::Illegal,
            isa_constraint: IsaConstraint::$const,
            category: Category::B,
        })
    };
}

macro_rules! opc {
    ($opc:ident, $format:ident) => {
        Some(OpcodeRecord {
            lookup: PrimaryLookup::Opc(Opcode::$opc, Format::$format),
            isa_constraint: IsaConstraint::All,
            category: Category::B,
        })
    };
    ($opc:ident, $format:ident, $constraint:ident) => {
        Some(OpcodeRecord {
            lookup: PrimaryLookup::Opc(Opcode::$opc, Format::$format),
            isa_constraint: IsaConstraint::$constraint,
            category: Category::B,
        })
    };
}

// PPC: instructions defined by PowerPC (ref: `SR28-5124-01_The_PowerPC_Architecture_May94.pdf`)
//
// some weird details incldue, "has `fres`, does not have `fre`". for another example, see
// `frsqrtes`, which presumably is 2.01 later or ...something?
macro_rules! ppc {
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, Ppc)
    };
}

macro_rules! p202 {
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, PowerIsa202)
    };
}
macro_rules! p203 {
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, PowerIsa203)
    };
}
macro_rules! p206 {
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, PowerIsa206)
    };
}

macro_rules! p207 {
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, PowerIsa207)
    };
}

// DFP: Decimal Floating-Point
macro_rules! dfp {
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, DFP)
    };
}
macro_rules! dfp25 {
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, DFP25)
    };
}
macro_rules! dfp26 {
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, DFP26)
    };
}
macro_rules! dfp27 {
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, DFP27)
    };
}
// DFPQA: Decimal Floating-Point Quantum Adjust, defined in Power ISA v2.05
macro_rules! dfpqa {
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, DFPQA)
    };
}

#[derive(Copy, Clone, PartialEq, Eq)]
struct ExtensionTable {
    records: &'static [Option<OpcodeRecord>],
    bit_offset: u8,
    bit_count: u8,
}

impl ExtensionTable {
    fn extract_idx(&self, word: u32) -> usize {
        let mask = (1 << self.bit_count) - 1;
        ((word >> self.bit_offset) & mask) as usize
    }
}

// in at least Power ISA v3.0 (`PowerISA_public.v3.0B.pdf`), appendix D
// > Power ISA Instruction Set Sorted by Opcode
// includes a helpful column "Version" enumerating what versions each still-in-v3.00 instruction
// was added.
#[allow(non_camel_case_types)]
#[derive(Copy, Clone, PartialEq, Eq, Debug)]
enum IsaConstraint {
    // PowerPC "AS" and later
    //
    // this is a handful of adjustments on PowerPC that were made for the Amazon processors in
    // some versions of the AS/400 as well as later IBM i systems. namely, this is morally similar
    // to "PowerPC + Slb"
    // PowerPC_AS,

    // PowerPC "P" and later
    //
    // this is effectively just "PowerPC everywhere else", so it's not actually been used below.
    // PowerPC_P,

    // only in original POWER (RS/6000)
    // .. no instructions here, afaik.
    //
    POWER,

    // only in POWER2 (not POWER, not PowerPC?)
    POWER2,
    // POWER2
    LE_POWER2,

    // Power V2.00
    //
    // this generally matches with the Power Amazon processors in the RS/6000.
    PowerIsa200,

    // Power V2.02
    //
    // this controls relatively few details, but bclr/bcctr/etc use of the BH field to control
    // prediction hints were added somewhere between PowerPC 1994 and v2.02.
    PowerIsa202,

    // Power V2.03
    //
    // in many cases this added new instructions, but for some instructions (DBCT, DBCTST) being at
    // this version or later implies an additional hint operand.
    PowerIsa203,

    // Power V2.05
    PowerIsa205,

    // Power V2.06
    PowerIsa206,

    // implementations including an FPU.
    //
    // this is generally all of them, but notably the e500 did not.
    Fpu,

    // implementations including an FPU that supports single-precision floats.
    //
    // notably RIOS did not support single-precision floats, and they only came along in PowerPC?
    // this surprising fact brought to you by the RS/6000 Hardware Technical Reference not
    // describing any instruction under opcode 59 and objdump agreeing with it.
    FpuNoSingle,

    // support for the `isel` instruction.
    //
    // the support of `isel` is *curious*. and certainly not mainline until POWER7 aka v2.06.
    Isel,

    // BTB locking instructions
    //
    // these are BBLELS and BBELR, which (so far as I know) only existed on PowerPC e500
    Btb,

    // SLB management instructions
    //
    // these are SLBIE and SLBIA, which are optional as of the 1994 PowerPC manual, but not
    // described as optional in v2.02 or later. Xenon does not include them.
    Slb,

    // segment register manipulation instructions
    //
    // these are MTSR, MTSRIN, MFSR, MFSRIN, as well as the removed MTSRD, MTSRDIN. this set of
    // instructions became optional with PowerPC. Xenon and Gekko (+Broadway) opts to not have them.
    Seg,

    // external control instructions
    //
    // these are part of the Virtual ISA, and some processors (Xenon) do not care about them.
    Ec,

    // instructions to return from interrupts.
    //
    // these are RFI, RFID. they are seemingly in AS and PowerPC, but not Xenon?
    Rfi,

    // TLB management instructions
    //
    // these are TLBIE, TLBIA, TLBSYNC. these are part of the Virtual ISA, and some processors
    // (Xenon) do not care about them.
    Tlb,

    // software TLB management instructions
    //
    // the extact TLB management instructions vary across (especially earlier) Power ISA
    // processors. TlbSw is a subset of instructions used in e200, e500, etc for TLB management
    // which were less common. these are generally derived from the AIX 5.3 manual as well.
    TlbSw,

    // only in Power implementations for "embedded" uses
    //
    // this was an option in v2.03 and later implementations, but removed by Power ISA v3.0.
    //
    // some instructiosn in Embedded overlap with non-embedded instructions, so for IsaVersion that
    // overlap with this support it's possible that were previously ignored fields are instead used
    // to pick alternate opcodes. instructions *were* in Embedded, removed, and not interpreted in
    // a different way later, are reported as their Embedded form under IsaVersion::All
    Embedded,

    // only in Power implementations which include AltiVec (Motorola G4, Cell, Xenon)
    //
    // Xenon is interesting in that it supports AltiVec instructions *and* VMX128, below.
    //
    // TODO: this is assumed to be equivalent to the Vector category in v2.06+
    AltiVec,

    // only in implementations which include AltiVec, but before AltiVec was made part of the Power
    // ISA.
    //
    // the relevant instructions here are described in
    //
    // > ALTIVECPOWERISAPEM, AltiVec Technology Programming Environments Manual
    //
    // and encompass `dss`, `dssall`, `dst`, `dstst`, and `dststt`.
    AltiVec_NonPower,

    // only in Power implementations which include AltiVec, but removed in v2.06
    //
    // TODO: does Cell support these? probably...
    AltiVec_LE206,

    // Xenon
    VMX128,

    // a handful of cases where at least xenia goes beyond the manual (see `sc`), unsure what
    // hardware actually supports or not.
    Xenon,

    // and in even fewer cases, an instruction is known to Xenia and at least RPCS3 so it is
    // presumably in Cell *and* Xenon, but not documented in any manuals.
    CellOrXenon,

    // outside opc4, a few instructions are either gekko-only or have bytes interpreted differently
    // by gekko/broadway
    Gekko,

    // only in Power implementations which extended VMX to VSX (Power >=v2.06, POWER7)
    VSX,

    // > LMA: Legacy Integer Multiply-Accumulate
    LMA,

    // Power implementations that include Decimal Floating-Point (Power >=v2.05, POWER6)
    //
    // some later implementations extend the set of instructions in Decimal Floating-Point, which
    // have later constraints.
    DFP,
    // Decimal Floating-Point Quantum Adjustment operations (Power >=v2.05)
    DFPQA,
    // Decimal Floating-Point additions for Power 2.05. instructions that are not part of specific
    // subdivisions of DFP but added in 2.05 all the same.
    DFP25,
    // Decimal Floating-Point additions for Power 2.06. among other things, this includes..
    // extended rounding mode control? see `drrnd` for one example.
    DFP26,
    // Decimal Floating-Point additions for Power 2.07
    DFP27,

    // PowerPC ("AP" in v2.01)
    //
    // notably, Gekko is here (as is Broadway)
    Ppc,

    // "Category: 64-bit", added in Power v2.06, but Xenia decodes these so i infer these were
    // likely present in other 64-bit PowerPC implementations..? Power v2.06 only has LDBRX/STDBRX
    // here.
    //
    // there *are* other 64-bit only instructions though, ldu, std, stdu, ...
    Ppc64,
    // Power ISA v2.07
    PowerIsa207,
    // Power ISA v3.0
    PowerIsa30,
    // actually all POWER revisions to date.
    All,
}

// "AltiVec™ Technology Programming Enviroments Manual, Rev. 3", `ALTIVECPEM.pdf`
// (`sha256: c16686d07e509cf059d9d11d7c3c807dea259497fc74d8fced41846f865406cd`) includes Appendix
// A.6 Instruction Set Legend, which describes which of UISA or VEA various instructions are in.
//
// UISA: .. all of them except
// VEA: DSS, DSSALL, DSTST, DSTSTT, DSTT

// appendix I. Opcode Maps in Power 2.01 document (ppc_isa.isa, sha256: TODO)
// describes what machines are applicable for a given definition with the following notation:
// * A: PowerPC
// * P: PowerPC
// * 2: POWER2
// * All: All of the above
//
// future manuals instead use this section of the opcode map to declare instruction *categories*
// which are defined in section `1.3.5 Categories`. reproduced below:
//
// * B: Base  ; Required for all implementations
// * S: Server ; Required for Server implementations
// * E: Embedded : Required for Embedded implementations
// * ATB: Alternate Time Base ; An additional Time Base; see Book II
// * CS: Cache Specification ; Specify a specific cache for some instructions; see Book II
// * DFP: Decimal Floating-Point ; Decimal Floating-Point facilities
// * DS: Decorated Storage ; Decorated Storage facilities
// * EMB: Elemental Memory Barriers ; More granular memory barrier support
// * E.CD: Embedded.Cache Debug ; Provides direct access to cache data and directory content
// * E.CI: Embedded.Cache Initialization ; Instructions that invalidate the entire cache
// * E.DC: Embedded.Device Control ; Legacy Device Control bus support
// * E.ED: Embedded.Enhanced Debug ; Embedded Enhanced Debug facility; see Book III-E
// * E.PD: Embedded.External PID ; Embedded External PID facility; see Book III-E
// * E.HV: Embedded.Hypervisor ; Embedded Logical Partitioning and hypervisor facilities
// * E.HV.LRAT: Embedded.Hypervisor.LRAT ; Embedded Hypervisor Logical to Real Address Translation facility; see Book III-E
// * E.LE: Embedded.Little-Endian ; Embedded Little-Endian page attribute; see Book III-E
// * E.MMUF: Embedded.MMU Type FSL ; Type FSL Storage Control
// * E.PT: Embedded.Page Table ; Embedded Page Table facility; see Book III-E
// * E.TWC: Embedded.TLB Write Conditional ; Embedded TLB Write Conditional facility; see Book III-E
// * E.PM: Embedded.Performance Monitor ; Embedded Performance Monitor example; see Book III-E
// * E.PC: Embedded.Processor Control ; Embedded Processor Control facility; see Book III-E
// * ECL: Embedded Cache Locking ; Embedded Cache Locking facility; see Book III-E
// * EM: Embedded Multi-Threading ; Embedded Multi-Threading; see Book III-E
// * EM.TM: Embedded Multi-Threading.Thread Management ; Embedded Multi-Threading Thread Management Facility
// * EC: External Control ; External Control facility; see Book II
// * EXP: External Proxy ; External Proxy facility; see Book III-E
// * FP: Floating-Point ; Floating-Point Facilities
// * FP: Floating-Point.Record ; Floating-Point instructions with Rc=1
// * LMA: Legacy Integer Multiply-Accumulate1 ; Legacy Integer Multiply-accumulate instructions
// * LMV: Legacy Move Assist ; Determine Left most Zero Byte instruction
// * LSQ: Load/Store Quadword ; Load/Store Quadword instructions; see Book III-S
// * MMC: Memory Coherence ; Requirement for Memory Coherence; see Book II
// * MA: Move Assist ; Move Assist instructions
// * PCR: Processor Compatibility ; Processor Compatibility Register
// * S.PM: Server.Performance Monitor ; Server Performance Monitor example; see Book III-S
// * S.PC: Server.Processor Control ; Server Processor Control Facility; see Book III-S
// * S.RPTA: Server.Relaxed Page Table Alignment ; HTAB alignment on 256 KB boundary; see Book III-S
// * SP: Signal Processing Engine1, 2 ; Facility for signal processing
// * SP.FD: SPE.Embedded Float Scalar Double ; GPR-based Floating-Point double-precision instruction set
// * SP.FS: SPE.Embedded Float Scalar Single ; GPR-based Floating-Point single-precision instruction set
// * SP.FV: SPE.Embedded Float Vector ; GPR-based Floating-Point Vector instruction set
// * SCPM: Store Conditional Page Mobility ; Store Conditional accounting for page movement; see Book II
// * STM: Stream ; Stream variant of dcbt instruction; see Book II
// * SAO: Strong Access Order ; Assist for X86 and Sparc emulation; see Book II
// * TRC: Trace ; Trace Facility ; see Book III-S
// * TM: Transactional Memory ; Full hardware Transactional Memory support
// * VLE: Variable Length Encoding ; Variable Length Encoding facility; see Book VLE
// * VSX: Vector-Scalar Extension ; Vector-Scalar Extension. Requires implementation of Floating-Point and Vector categories
// * V: Vector1 ; Vector facilities
// * V.LE: Vector.Little-Endian ; Little-Endian support for Vector storage operations.
// * V.GBB: Vector.Crypto ; Cryptographic instruction set
// * V.XOR: Vector.RAID ; Vector Permute-XOR instruction
// * WT: Wait ; wait instruction; see Book II
// * 64: 64-Bit ; Required for 64-bit implementations; not defined for 32-bit impl’s
//
// further, there are categories "Phased-In" and "Phased-Out" which are apparently not reported in opcode maps..?
//
// TODO: Category has since gone unused, and `IsaConstraint` has partially taken its place. the two
// should get rethought, probably?
#[allow(non_camel_case_types)]
#[allow(dead_code)]
#[derive(Copy, Clone, PartialEq, Eq, Debug)]
enum Category {
    // Base  ; Required for all implementations
    B,
    // Server ; Required for Server implementations
    S,
    // Embedded : Required for Embedded implementations
    E,
    // Alternate Time Base ; An additional Time Base; see Book II
    ATB,
    // Cache Specification ; Specify a specific cache for some instructions; see Book II
    CS,
    // Decimal Floating-Point ; Decimal Floating-Point facilities
    DFP,
    // Decorated Storage ; Decorated Storage facilities
    DS,
    // Elemental Memory Barriers ; More granular memory barrier support
    EMB,
    // Embedded.Cache Debug ; Provides direct access to cache data and directory content
    E_CD,
    // Embedded.Cache Initialization ; Instructions that invalidate the entire cache
    E_CI,
    // Embedded.Device Control ; Legacy Device Control bus support
    E_DC,
    // Embedded.Enhanced Debug ; Embedded Enhanced Debug facility; see Book III-E
    E_ED,
    // Embedded.External PID ; Embedded External PID facility; see Book III-E
    E_PD,
    // Embedded.Hypervisor ; Embedded Logical Partitioning and hypervisor facilities
    E_HV,
    // Embedded.Hypervisor.LRAT ; Embedded Hypervisor Logical to Real Address Translation facility; see Book III-E
    E_HV_LRAT,
    // Embedded.Little-Endian ; Embedded Little-Endian page attribute; see Book III-E
    E_LE,
    // Embedded.MMU Type FSL ; Type FSL Storage Control
    E_MMUF,
    // Embedded.Page Table ; Embedded Page Table facility; see Book III-E
    E_PT,
    // Embedded.TLB Write Conditional ; Embedded TLB Write Conditional facility; see Book III-E
    E_TWC,
    // Embedded.Performance Monitor ; Embedded Performance Monitor example; see Book III-E
    E_PM,
    // Embedded.Processor Control ; Embedded Processor Control facility; see Book III-E
    E_PC,
    // Embedded Cache Locking ; Embedded Cache Locking facility; see Book III-E
    ECL,
    // Embedded Multi-Threading ; Embedded Multi-Threading; see Book III-E
    EM,
    // Embedded Multi-Threading.Thread Management ; Embedded Multi-Threading Thread Management Facility
    EM_TM,
    // External Control ; External Control facility; see Book II
    EC,
    // External Proxy ; External Proxy facility; see Book III-E
    EXP,
    // Floating-Point ; Floating-Point Facilities
    FP,
    // Floating-Point.Record ; Floating-Point instructions with Rc=1
    FP_R,
    // Legacy Integer Multiply-Accumulate1 ; Legacy Integer Multiply-accumulate instructions
    LMA,
    // Legacy Move Assist ; Determine Left most Zero Byte instruction
    LMV,
    // Load/Store Quadword ; Load/Store Quadword instructions; see Book III-S
    LSQ,
    // Memory Coherence ; Requirement for Memory Coherence; see Book II
    MMC,
    // Move Assist ; Move Assist instructions
    MA,
    // Processor Compatibility ; Processor Compatibility Register
    PCR,
    // Server.Performance Monitor ; Server Performance Monitor example; see Book III-S
    S_PM,
    // Server.Processor Control ; Server Processor Control Facility; see Book III-S
    S_PC,
    // Server.Relaxed Page Table Alignment ; HTAB alignment on 256 KB boundary; see Book III-S
    S_RPTA,
    // Signal Processing Engine1, 2 ; Facility for signal processing
    SP,
    // SPE.Embedded Float Scalar Double ; GPR-based Floating-Point double-precision instruction set
    SP_FD,
    // SPE.Embedded Float Scalar Single ; GPR-based Floating-Point single-precision instruction set
    SP_FS,
    // SPE.Embedded Float Vector ; GPR-based Floating-Point Vector instruction set
    SP_FV,
    // Store Conditional Page Mobility ; Store Conditional accounting for page movement; see Book II
    SCPM,
    // Stream ; Stream variant of dcbt instruction; see Book II
    STM,
    // Strong Access Order ; Assist for X86 and Sparc emulation; see Book II
    SAO,
    // Trace ; Trace Facility ; see Book III-S
    TRC,
    // Transactional Memory ; Full hardware Transactional Memory support
    TM,
    // Variable Length Encoding ; Variable Length Encoding facility; see Book VLE
    VLE,
    // Vector-Scalar Extension ; Vector-Scalar Extension. Requires implementation of Floating-Point and Vector categories
    VSX,
    // Vector1 ; Vector facilities
    V,
    // Vector.Little-Endian ; Little-Endian support for Vector storage operations.
    V_LE,
    // Vector.Crypto ; Cryptographic instruction set
    V_GBB,
    // Vector.RAID ; Vector Permute-XOR instruction
    V_XOR,
    // Wait ; wait instruction; see Book II
    WT,
    // 64-Bit ; Required for 64-bit implementations; not defined for 32-bit impl’s
    B_64,
}

static CR_OPS: ExtensionTable = ExtensionTable {
    bit_offset: 1,
    bit_count: 10,
    records: &[
        // 0x0_00
        opc!(MCRF, XL), None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_10
        opc!(BCLR, XL), None, opc!(RFID, XL, Rfi), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_20
        None, opc!(CRNOR, XL), None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_30
        None, None, opc!(RFI, XL, Rfi) /* parens */, invalid!(Ppc), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_40
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_50
        None, None, opc!(RFSVC, XL, LE_POWER2), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_60
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_70
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_80
        None, opc!(CRANDC, XL), None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_90
        None, None, None, None, None, None, opc!(ISYNC, XL), None,
        None, None, None, None, None, None, None, None,
        // 0x0_a0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_b0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_c0
        None, opc!(CRXOR, XL), None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_d0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_e0
        None, opc!(CRNAND, XL), None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_f0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_00
        None, opc!(CRAND, XL), None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_10
        None, None, p202!(HRFID, XL), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_20
        None, opc!(CREQV, XL), None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_30
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_40
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_50
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_60
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_70
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_80
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_90
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_a0
        None, opc!(CRORC, XL), None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_b0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_c0
        None, opc!(CROR, XL), None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_d0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_e0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_f0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_00
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_10
        opc!(BCCTR, XL), None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_20
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_30
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_40
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_50
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_60
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_70
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_80
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_90
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_a0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_b0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_c0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_d0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_e0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_f0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_00
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_10
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_20
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_30
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_40
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_50
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_60
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_70
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_80
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_90
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_a0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_b0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_c0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_d0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_e0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_f0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
    ]
};

static FX_DWD_ROT: ExtensionTable = ExtensionTable {
    bit_offset: 1,
    bit_count: 4,
    records: &[
        opc!(RLDICL, MD, Ppc64), opc!(RLDICL, MD, Ppc64), opc!(RLDICR, MD, Ppc64), opc!(RLDICR, MD, Ppc64),
        opc!(RLDIC, MD, Ppc64), opc!(RLDIC, MD, Ppc64), opc!(RLDIMI, MD, Ppc64), opc!(RLDIMI, MD, Ppc64),
        opc!(RLDCL, MDS, Ppc64), opc!(RLDCR, MDS, Ppc64), None, None,
        None, None, None, None,
    ]
};

// AltiVec OP
macro_rules! avop {
    ($opc:ident) => {
        opc!($opc, VX, AltiVec)
    };
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, AltiVec)
    };
}

// VSX OP
/*
macro_rules! vop {
    ($opc:ident) => {
        opc!($opc, VX, VSX)
    };
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, VSX)
    };
}
*/

macro_rules! lma {
    ($opc:ident) => {
        opc!($opc, XO, LMA)
    };
    ($opc:ident, $format:ident) => {
        opc!($opc, $format, LMA)
    };
}
// in at least Power v2.06+ the extension tables were expanded to include bit 31, which previously
// was used for Lk, Rc, etc per-instruction. the semantic of this bit is unchanged, and so for
// table concision (aka "i'm lazy") i'm leaving handling of that bit to after the table lookup.
//
// the remaining parts of `table_section == 0b00 or 0b01`. the low bit is compressed out,
// and the high bit of table section is compressed out, so only 9 bits are needed to index
// the table.
//
// in Power 2.07 and above many additional entries here become valid as VSX had many additions.
static VECTOR_LMA: ExtensionTable = ExtensionTable {
    bit_offset: 0,
    bit_count: 11,
    // the records here are an interleaving of `Table 8: (Left)` and `Table 8: (Center-Left)`
    records: &[
        // 0x0_00
        avop!(VADDUBM), avop!(VMAXUB), avop!(VRLB), avop!(VCMPEQUB, VC), avop!(VMULOUB), avop!(VADDFP), avop!(VMRGHB), avop!(VPKUHUM),
        // 0x0_20
        lma!(MULHHWU), None,         None,       None,           lma!(MACHHWU, XO), None,     None,         None,
        // 0x0_40
        avop!(VADDUHM), avop!(VMAXUH), avop!(VRLH), avop!(VCMPEQUH, VC), avop!(VMULOUH), avop!(VSUBFP), avop!(VMRGHH), avop!(VPKUWUM),
        // 0x0_60
        lma!(MULHHWW), None,         None,       None,           lma!(MACHHW, XO),  None,     lma!(NMACHHW),None,
        // 0x0_80
        avop!(VADDUWM), avop!(VMAXUW), avop!(VRLW), avop!(VCMPEQUW, VC), None, None, avop!(VMRGHW), avop!(VPKUHUS),
        // 0x0_a0
        None,          None,         None,       None,         /*TODO: "long" */  None,          None,         None,         None,
        // 0x0_c0
        None,          None,         None,       avop!(VCMPEQFP, VC), None, None, None, avop!(VPKUWUS),
        // 0x0_e0
        None,          None,         None,       None,           lma!(MACHHWS, XO), None,     /*TODO: "long" */ None,         None,
        // 0x1_00
        None,          avop!(VMAXSB), avop!(VSLB), None, avop!(VMULOSB), avop!(VREFP),     avop!(VMRGLB), avop!(VPKSHUS),
        // 0x1_20
        lma!(MULCHWU), None,         None,       None,           lma!(MACCHWU, XO),          None,         None,         None,
        // 0x1_40
        None,          avop!(VMAXSH), avop!(VSLH), None, avop!(VMULOSH), avop!(VRSQRTEFP), avop!(VMRGLH), avop!(VPKSWUS),
        // 0x1_60
        lma!(MULCHW),  None,         None,       None,           lma!(MACCHW, XO),           lma!(NMACCHW, XO),  /*TODO: "long" */ None,         None,
        // 0x1_80
        avop!(VADDCUW), avop!(VMAXSW), avop!(VSLW), None, None,          avop!(VEXPTEFP),  avop!(VMRGLW), avop!(VPKSHSS),
        // 0x1_a0
        None,          None,         None,       None,           /*TODO: "long" */None,          None,         None,         None,
        // 0x1_c0
        None,          None,         avop!(VSL),  avop!(VCMPGEFP, VC),None, avop!(VLOGEFP),   None,         avop!(VPKSWSS),
        // 0x1_e0
        None,          None,         None,       None,           lma!(MACCHWS, XO),          None,         /*TODO: "long" */ None,         None,
        // 0x2_00
        avop!(VADDUBS), avop!(VMINUB), avop!(VSRB), avop!(VCMPGTUB, VC), avop!(VMULEUB), avop!(VRFIN), avop!(VSPLTB), avop!(VUPKHSB),
        // 0x2_20
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x2_40
        avop!(VADDUHS), avop!(VMINUH), avop!(VSRH), avop!(VCMPGTUH, VC), avop!(VMULEUH), avop!(VRFIZ), avop!(VSPLTH), avop!(VUPKHSH),
        // 0x2_60
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x2_80
        avop!(VADDUWS), avop!(VMINUW), avop!(VSRW), avop!(VCMPGTUW, VC), None,          avop!(VRFIP), avop!(VSPLTW), avop!(VUPKLSB),
        // 0x2_a0
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x2_c0
        None,          None,         avop!(VSR),  avop!(VCMPGTFP, VC), None,          avop!(VRFIM), None,         avop!(VUPKLSH),
        // 0x2_e0
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x3_00
        avop!(VADDSBS), avop!(VMINSB), avop!(VSRAB),avop!(VCMPGTSB, VC), avop!(VMULESB), avop!(VCFUX), avop!(VSPLTISB), avop!(VPKPX),
        // 0x3_20
        lma!(MULLHWU), None,         None,       None,           lma!(MACLHWU, XO),          None,         None,         None,
        // 0x3_40
        avop!(VADDSHS), avop!(VMINSH), avop!(VSRAH),avop!(VCMPGTSH, VC), avop!(VMULESH), avop!(VCFSX), avop!(VSPLTISH), avop!(VUPKHPX),
        // 0x3_60
        lma!(MULLHW),  None,         None,       None,           lma!(MACLHW, XO),           None,         lma!(NMACLHW, XO),         None,
        // 0x3_80
        avop!(VADDSWS), avop!(VMINSW), avop!(VSRAW),avop!(VCMPGTSW, VC), None,          avop!(VCTUXS),avop!(VSPLTISW), None,
        // 0x3_a0
        None,          None,         None,       None,           /*TODO: "long" */ None,          None,         None,         None,
        // 0x3_c0
        None,          None,         None,       avop!(VCMPBFP, VC),  None,          avop!(VCTSXS),None,           avop!(VUPKLPX),
        // 0x3_e0
        None,          None,         None,       None,           lma!(MACLHWS, XO),          None,         /*TODO: "long" */ None,         None,
        // 0x4_00
        // DOC BUG: Power ISA manuals before V3.0 had an error in Table 8 that
        // swapped VAVGUB, VAVGUH, and VAVGUW, ordering them as VAVGUH, VAVGUW, VAVGUB. their
        // extended opcodes in the table did not match the extended opcodes in the instruction
        // descriptions, either. unfortunate.
        avop!(VSUBUBM), avop!(VAVGUB), avop!(VAND), avop!(VCMPEQUB, VCdot),
                                                                 None,          avop!(VMAXFP), avop!(VSLO), None,
        // 0x4_20
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x4_40
        avop!(VSUBUHM), avop!(VAVGUH), avop!(VANDC),avop!(VCMPEQUH, VCdot),
                                                                 None,          avop!(VMINFP), avop!(VSRO), None,
        // 0x4_60
        None,          None,         None,       None,           lma!(MACHHW /* TODO: prime */, XO),          None,         None,         None,
        // 0x4_80
        avop!(VSUBUWM), avop!(VAVGUW), avop!(VOR),  avop!(VCMPEQUW, VCdot), None,   None,         None,       None,
        // 0x4_a0
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x4_c0
        None,          None,         avop!(VXOR), avop!(VCMPEQFP, VCdot), None,   None,         None,       None,
        // 0x4_e0
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x5_00
        None,          avop!(VAVGSB), avop!(VNOR), None,           None,          None,         None,       None,
        // 0x5_20
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x5_40
        None,          avop!(VAVGSH), None,       None,           None,          None,         None,       None,
        // 0x5_60
        None,          None,         None,       None,           lma!(MACCHW /* TODO: prime */, XO),          None,         None,         None,
        // 0x5_80
        avop!(VSUBCUW), avop!(VAVGSW), None,       None,           None,          None,         None,       None,
        // 0x5_a0
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x5_c0
        None,          None,         None,       avop!(VCMPGEFP, VCdot), None,   None,         None,       None,
        // 0x5_e0
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x6_00
        avop!(VSUBUBS), None,         avop!(MFVSCR),avop!(VCMPGTUB, VCdot), avop!(VSUM4UBS),   None,         None,       None,
        // 0x6_20
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x6_40
        avop!(VSUBUHS), None,         avop!(MTVSCR),avop!(VCMPGTUH, VCdot), avop!(VSUM4SHS),   None,         None,       None,
        // 0x6_60
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x6_80
        avop!(VSUBUWS), None,         None,       avop!(VCMPGTUW, VCdot), avop!(VSUM2SWS),    None,         None,       None,
        // 0x6_a0
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x6_c0
        None,          None,         None,       avop!(VCMPGTFP, VCdot), None,              None,         None,       None,
        // 0x6_e0
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x7_00
        avop!(VSUBSBS), None,         None,       avop!(VCMPGTSB, VCdot), avop!(VSUM4SBS),    None,         None,       None,
        // 0x7_20
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x7_40
        avop!(VSUBSHS), None,         None,       avop!(VCMPGTSH, VCdot), None,              None,         None,       None,
        // 0x7_60
        None,          None,         None,       None,           lma!(MACLHW /* TODO: prime */, XO),          None,         None,         None,
        // 0x7_80
        avop!(VSUBSWS), None,         None,       avop!(VCMPGTSW, VCdot), avop!(VSUMSWS),     None,         None,       None,
        // 0x7_a0
        None,          None,         None,       None,           None,          None,         None,         None,
        // 0x7_c0
        None,          None,         None,       avop!(VCMPBFP, VCdot),  None,              None,         None,       None,
        // 0x7_e0
        None,          None,         None,       None,           None,          None,         None,         None,
    ]
};

static FX_EXTENDED_OPS: ExtensionTable = ExtensionTable {
    bit_offset: 1,
    bit_count: 10,
    records: &[
        // 0x0_00
        opc!(CMP, X), None, None, None, opc!(TW, X), None, avop!(LVSL, X), avop!(LVEBX, X),
        opc!(SUBFC, XO), opc!(MULHDU, XO, Ppc64), opc!(ADDC, XO), opc!(MULHWU, XO, Ppc), None, None, None, opc!(ISEL, A, Isel),
        // 0x0_10
        None, None, None, opc!(MFCR, XFX), opc!(LWARX, X, Ppc), opc!(LDX, X, Ppc64), None, opc!(LWZX, X),
        opc!(SLW, X), None, opc!(CNTLZW, X), opc!(SLD, X, Ppc64), opc!(AND, X), opc!(MASKG, X, LE_POWER2), None /* RLDICL* */, None,
        // 0x0_20
        opc!(CMPL, X), None, None, None, None, None, avop!(LVSR, X), avop!(LVEHX, X),
        opc!(SUBF, XO, Ppc), None, None, None, None, None, None, opc!(ISEL, A, Isel),
        // 0x0_30
        None, None, None, None, None, opc!(LDUX, X, Ppc64), opc!(DCBST, X, Ppc), opc!(LWZUX, X),
        None, None, opc!(CNTLZD, X, Ppc64), None, opc!(ANDC, X), None, None /* asterisk */ , None,
        // 0x0_40
        None, None, None, None, opc!(TD, X, Ppc64), None, None, avop!(LVEWX, X),
        None, opc!(MULHD, XO, Ppc64), None, opc!(MULHW, XO, Ppc), None, None, None, opc!(ISEL, A, Isel),
        // 0x0_50
        None, None, opc!(MTSRD, X, Seg), opc!(MFMSR, X), opc!(LDARX, X, Ppc64), None, opc!(DCBF, X, Ppc), opc!(LBZX, X),
        None, None, None, None, None, None, None /* asterisk */, None,
        // 0x0_60
        None, None, None, None, None, None, None, avop!(LVX, X),
        opc!(NEG, XO), None, None, opc!(MUL, XO, LE_POWER2), None, None, None, opc!(ISEL, A, Isel),
        // 0x0_70
        None, None, opc!(MTSRDIN, X, Seg), None, None, None, opc!(CLF, X, LE_POWER2), opc!(LBZUX, X),
        None, None, None, None, opc!(NOR, X), None, None /* asterisk */, None,
        // 0x0_80
        None, None, None, p207!(WRTEE, E /* TODO: not sure where this was added, after PPC, before 2.07? */), None, None, None, avop!(STVEBX, X),
        opc!(SUBFE, XO), None, opc!(ADDE, XO), None, None, None, p207!(MSGSNDP, X), opc!(ISEL, A, Isel),
        // 0x0_90
        opc!(MTCRF, XFX), None, opc!(MTMSR, X), None, None, opc!(STDX, X, Ppc64), opc!(STWCX, X, Ppc), opc!(STWX, X),
        opc!(SLQ, X, LE_POWER2), opc!(SLE, X, LE_POWER2), None, None, None, None, None /* RLDIC* */, None /* opcode 31 ext 62 RLWIMI* */,
        // 0x0_a0
        None, None, None, p207!(WRTEEI, E /* TODO: not sure where this was added, after PPC, before 2.07? */), None, None, p203!(DCBTLS, X), avop!(STVEHX, X),
        None, None, None, None, None, None, p207!(MSGCLRP, X), opc!(ISEL, A, Isel),
        // 0x0_b0
        None, None, opc!(MTMSRD, X, Ppc64), None, None, opc!(STDUX, X, Ppc64), None, opc!(STWUX, X),
        opc!(SLIQ, X, LE_POWER2), None, None, None, None, None, None /* RLDIC* */, None /* RLWINM* */,
        // 0x0_c0
        None, None, None, None, None, None, None, avop!(STVEWX, X),
        opc!(SUBFZE, XO), None, opc!(ADDZE, XO), None, None, None, p207!(MSGSND, X), opc!(ISEL, A, Isel),
        // 0x0_d0
        None, None, opc!(MTSR, X, Seg), None, None, None, opc!(STDCX, X, Ppc64), opc!(STBX, X),
        opc!(SLLQ, X, LE_POWER2), opc!(SLEQ, X, LE_POWER2), None, None, None, None, None /* RLDIMI* */, None /* opcode 31 shadow RLMI* */,
        // 0x0_e0
        None, None, None, None, None, None, None, avop!(STVX, X),
        opc!(SUBFME, XO), opc!(MULLD, XO, Ppc64), opc!(ADDME, XO), opc!(MULLW, XO), None, None, p207!(MSGCLR, X), opc!(ISEL, A, Isel),
        // 0x0_f0
        None, None, opc!(MTSRIN, X, Seg), None, None, None, opc!(DCBTST, X), opc!(STBUX, X),
        opc!(SLLIQ, X, LE_POWER2), None, None, None, None, None, None /* RLDIMI* */, None /* RLWNM* */,
        // 0x1_00
        None, None, None, None, None, None, invalid!(Ppc), None,
        opc!(DOZ, XO, LE_POWER2), None, opc!(ADD, XO), None, None, None, None, opc!(ISEL, A, Isel),
        // 0x1_10
        None, None, invalid!(Ppc), None, None, opc!(LSCBX, X, LE_POWER2), opc!(DCBT, X), opc!(LHZX, X),
        None, None, None, None, opc!(EQV, X), None, None /* RLDCL* */, None /* ORI* */,
        // 0x1_20
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, opc!(ISEL, A, Isel),
        // 0x1_30
        None, None, opc!(TLBIE, X), None, invalid!(Ppc), None, opc!(ECIWX, X, Ec), opc!(LHZUX, X),
        None, None, None, None, opc!(XOR, X), None, None /* RLDCR* */, None /* ORIS */,
        // 0x1_40
        None, None, None, invalid!(Ppc), None, None, None, None,
        None, None, None, opc!(DIV, XO, LE_POWER2), None, None, None, opc!(ISEL, A, Isel),
        // 0x1_50
        None, None, None, opc!(MFSPR, XFX), None, opc!(LWAX, X, Ppc64), opc!(DST, X, AltiVec_NonPower), opc!(LHAX, X),
        None, None, None, None, None, None, None, None /* XORI* */,
        // 0x1_60
        None, None, None, None, None, None, None, avop!(LVXL, X),
        opc!(ABS, XO, LE_POWER2), None, None, opc!(DIVS, XO, LE_POWER2), None, None, None, opc!(ISEL, A, Isel),
        // 0x1_70
        None, None, opc!(TLBIA, X, Tlb), opc!(MFTB, XFX, Ppc), None, opc!(LWAUX, X, Ppc64), opc!(DSTST, X, AltiVec_NonPower), opc!(LHAUX, X),
        None, None, None, None, None, None, None, None /* XORIS* */,
        // 0x1_80
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, opc!(ISEL, A, Isel),
        // 0x1_90
        None, None, opc!(SLBMTE, X, Slb), None, None, None, None, opc!(STHX, X),
        None, None, None, None, opc!(ORC, X), None, None, None /* ANDI* */,
        // 0x1_a0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, opc!(ISEL, A, Isel),
        // 0x1_b0
        None, None, opc!(SLBIE, X, Slb), None, None, None, opc!(ECOWX, X, Ec), opc!(STHUX, X),
        None, None, None, None, opc!(OR, X), None, None, None /* ANDIS* */,
        // 0x1_c0
        None, None, None, invalid!(Ppc), None, None, invalid!(Ppc), None,
        None, opc!(DIVDU, XO, Ppc64), None, opc!(DIVWU, XO, Ppc), None, None, None, opc!(ISEL, A, Isel),
        // 0x1_d0
        None, None, None, opc!(MTSPR, XFX), None, None, opc!(DCBI, X, Ppc) /* parens */, None /* LMW* */,
        None, None, None, None, opc!(NAND, X), None, None, None,
        // 0x1_e0
        None, None, None, None, None, None, invalid!(Ppc), avop!(STVXL, X),
        opc!(NABS, XO, LE_POWER2), opc!(DIVD, XO, Ppc64), None, opc!(DIVW, XO, Ppc), None, None, None, opc!(ISEL, A, Isel),
        // 0x1_f0
        None, None, opc!(SLBIA, X, Slb), None, None, None, opc!(CLI, X, LE_POWER2), None /* STMW* */,
        None, None, None, None, None, None, None, None,
        // 0x2_00
        opc!(MCRXR, X), None, None, None, None, None, opc!(BBLELS, X, Btb), opc!(LVLX, X, AltiVec_LE206),
        opc!(SUBFC, XO), opc!(MULHDU, XO, Ppc64), opc!(ADDC, XO), opc!(MULHWU, XO, Ppc), None, None, None, opc!(ISEL, A, Isel),
        // 0x2_10
        None, None, None, opc!(CLCS, X, LE_POWER2), opc!(LDBRX, X, Ppc64), opc!(LSWX, X), opc!(LWBRX, X), opc!(LFSX, X, Fpu),
        opc!(SRW, X), opc!(RRIB, X, LE_POWER2), None, opc!(SRD, X, Ppc64), None, opc!(MASKIR, X, LE_POWER2), None, None,
        // 0x2_20
        None, None, None, None, None, None, opc!(BBELR, X, Btb), opc!(LVRX, X, AltiVec_LE206),
        opc!(SUBF, XO, Ppc), None, None, None, None, None, None, opc!(ISEL, A, Isel),
        // 0x2_30
        None, None, None, None, None, None, opc!(TLBSYNC, X, Tlb), opc!(LFSUX, X, Fpu),
        None, None, None, None, None, None, None, None,
        // 0x2_40
        None, None, None, None, None, None, None, None,
        None, opc!(MULHD, XO, Ppc64), None, opc!(MULHW, XO, Ppc), None, None, None, opc!(ISEL, A, Isel),
        // 0x2_50
        None, None, None, opc!(MFSR, X, Seg), None, opc!(LSWI, X), opc!(SYNC, X), opc!(LFDX, X),
        None, None, None, None, None, None, None, None,
        // 0x2_60
        None, None, None, opc!(LDDX, X), None, None, None, None,
        opc!(NEG, XO), None, None, opc!(MUL, X, LE_POWER2), None, None, None, opc!(ISEL, A, Isel),
        // 0x2_70
        None, None, None, opc!(MFSRI, X, LE_POWER2), None, None, opc!(DCLST, X, LE_POWER2), opc!(LFDUX, X, Fpu),
        None, None, None, None, None, None, None, None,
        // 0x2_80
        None, None, None, None, None, None, None, opc!(STVLX, X, AltiVec_LE206),
        opc!(SUBFE, XO), None, opc!(ADDE, XO), None, None, None, p207!(TBEGIN, X), opc!(ISEL, A, Isel),
        // 0x2_90
        None, None, None, opc!(MFSRIN, X, Seg), opc!(STDBRX, X, Ppc64), opc!(STSWX, X), opc!(STWBRX, X), opc!(STFSX, X, Fpu),
        opc!(SRQ, X, LE_POWER2), opc!(SRE, X, LE_POWER2), None, None, None, None, None, None,
        // 0x2_a0
        None, None, None, None, None, None, None, opc!(STVRX, X, AltiVec_LE206),
        None, None, None, None, None, None, p207!(TEND, X), opc!(ISEL, A, Isel),
        // 0x2_b0
        None, None, None, None, None, None, None, opc!(STFSUX, X),
        opc!(SRIQ, X, LE_POWER2), None, None, None, None, None, None, None,
        // 0x2_c0
        None, None, None, None, None, None, None, None,
        opc!(SUBFZE, XO), None, opc!(ADDZE, XO), None, None, None, p207!(TCHECK, X), opc!(ISEL, A, Isel),
        // 0x2_d0
        None, None, None, None, None, opc!(STSWI, X), None, opc!(STFDX, X, Fpu),
        opc!(SRLQ, X, LE_POWER2), opc!(SREQ, X, LE_POWER2), None, None, None, None, None, None,
        // 0x2_e0
        None, None, None, None, None, None, None, None,
        opc!(SUBFME, XO), opc!(MULLD, XO, Ppc64), opc!(ADDME, XO), opc!(MULLW, XO), None, None, p207!(TSR, X), opc!(ISEL, A, Isel),
        // 0x2_f0
        None, None, None, None, None, None, p203!(DCBA, X) /* parens */, opc!(STFDUX, X),
        opc!(SRLIQ, X, LE_POWER2), None, None, None, None, None, None, None,
        // 0x3_00
        None, None, None, None, None, None, None, opc!(STVEPXL, X),
        opc!(DOZ, XO, LE_POWER2), None, opc!(ADD, XO), None, None, None, p207!(TABORTWC, X), opc!(ISEL, A, Isel),
        // 0x3_10
        None, None, opc!(TLBIVAX, X, TlbSw), None, None, None, opc!(LHBRX, X), opc!(LFDPX, X),
        opc!(SRAW, X), None, opc!(SRAD, X, Ppc64), None, None, None, None, None,
        // 0x3_20
        None, None, None, None, None, None, None, opc!(STVEPX, X),
        None, None, None, None, None, None, p207!(TABORTDC, X), opc!(ISEL, A, Isel),
        // 0x3_30
        None, None, opc!(RAC, X, LE_POWER2), None, None, None, opc!(DSS, X, AltiVec_NonPower), opc!(LFQUX, X, POWER2),
        opc!(SRAWI, X), None, opc!(SRADI, XS, Ppc64), opc!(SRADI, XS, Ppc64), None, None, None, None,
        // 0x3_40
        None, None, None, None, None, None, None, None,
        None, None, None, opc!(DIV, XO, LE_POWER2), None, None, p207!(TABORTWCI, X), opc!(ISEL, A, Isel),
        // 0x3_50
        None, None, None, opc!(SLBMFEV, X, Slb), None, None, opc!(EIEIO, X, Ppc), None,
        None, None, None, None, None, None, None, None,
        // 0x3_60
        None, None, None, None, None, None, None, None,
        opc!(ABS, XO, LE_POWER2), None, None, opc!(DIVS, XO, LE_POWER2), None, None, p207!(TABORTDCI, X), opc!(ISEL, A, Isel),
        // 0x3_70
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_80
        None, None, None, None, None, None, None, avop!(STVLXL, X),
        None, None, None, None, None, None, p207!(TABORT, X), opc!(ISEL, A, Isel),
        // 0x3_90
        None, None, opc!(TLBSX, X, TlbSw), opc!(SLBMFEE, X, Slb), None, None, opc!(STHBRX, X), opc!(STFDPX, X),
        opc!(SRAQ, X, LE_POWER2), opc!(SREA, X, LE_POWER2), opc!(EXTSH, X), None, None, None, None, None,
        // 0x3_a0
        None, None, None, None, None, None, None, avop!(STVRXL, X),
        None, None, None, None, None, None, p207!(TRECLAIM, X), opc!(ISEL, A, Isel),
        // 0x3_b0
        None, None, opc!(TLBRE, X, TlbSw), None, None, None, None, opc!(STFQUX, X, POWER2),
        opc!(SRAIQ, X, LE_POWER2), None, opc!(EXTSB, X, Ppc), None, None, None, None, None,
        // 0x3_c0
        None, None, None, None, None, None, invalid!(Ppc), None,
        None, opc!(DIVDU, XO, Ppc64), None, opc!(DIVWU, XO, Ppc), None, None, None, opc!(ISEL, A, Isel),
        // 0x3_d0
        None, None, opc!(TLBWE, X, TlbSw), None, None, None, opc!(ICBI, X, Ppc), opc!(STFIWX, X, Ppc),
        None, None, opc!(EXTSW, X, Ppc64), None, None, None, None, None,
        // 0x3_e0
        None, None, None, None, None, None, invalid!(Ppc), None,
        opc!(NABS, XO, LE_POWER2), opc!(DIVD, XO, Ppc64), None, opc!(DIVW, XO, Ppc), None, None, p207!(TRECHKPT, X), opc!(ISEL, A, Isel),
        // 0x3_f0
        None, None, invalid!(Ppc), None, None, None, ppc!(DCBZ, X), None,
        None, None, None, None, None, None, None, None,
    ]
};

static FX_DS_LOADS: ExtensionTable = ExtensionTable {
    bit_offset: 0,
    bit_count: 2,
    records: &[
        opc!(LD, DS, Ppc64), opc!(LDU, DS, Ppc64), opc!(LWA, DS, Ppc64), None,
    ]
};

static FX_DS_STORES: ExtensionTable = ExtensionTable {
    bit_offset: 0,
    bit_count: 2,
    records: &[
        opc!(STD, DS, Ppc64), opc!(STDU, DS, Ppc64), None, None,
    ]
};

static FP_SINGLE_EXTENDED_OPS: ExtensionTable = ExtensionTable {
    bit_offset: 1,
    bit_count: 10,
    records: &[
        // 0x0_00
        None, None, dfp!(DADD, X), dfpqa!(DQUA, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_10
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x0_20
        None, None, dfp!(DMUL, X), dfpqa!(DRRND, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_30
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x0_40
        None, None, dfp!(DSCLI, Z22), dfpqa!(DQUAI, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_50
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x0_60
        None, None, dfp!(DSCRI, Z22), dfpqa!(DRINTX, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_70
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x0_80
        None, None, dfp!(DCMPO, X), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_90
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x0_a0
        None, None, dfp25!(DTSTEX, X), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_b0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x0_c0
        None, None, dfp25!(DTSTDC, Z22), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_d0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x0_e0
        None, None, dfp25!(DTSTDG, Z22), dfpqa!(DRINTN, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_f0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x1_00
        None, None, dfp!(DCTDP, X), dfpqa!(DQUA, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_10
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x1_20
        None, None, dfp!(DCTFIX, X), dfpqa!(DRRND, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_30
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x1_40
        None, None, dfp!(DDEDPD, X), dfpqa!(DQUAI, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_50
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x1_60
        None, None, dfp!(DXEX, X), dfpqa!(DRINTX, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_70
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x1_80
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_90
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x1_a0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_b0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x1_c0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_d0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x1_e0
        None, None, None, dfpqa!(DRINTN, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_f0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x2_00
        None, None, dfp!(DSUB, X), dfpqa!(DQUA, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_10
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x2_20
        None, None, dfp!(DDIV, X), dfpqa!(DRRND, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_30
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x2_40
        None, None, dfp26!(DSCLI, Z22), dfpqa!(DQUAI, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_50
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x2_60
        None, None, dfp26!(DSCRI, Z22), dfpqa!(DRINTX, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_70
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x2_80
        None, None, dfp!(DCMPU, X), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_90
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x2_a0
        None, None, dfp25!(DTSTSF, X), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_b0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x2_c0
        None, None, dfp25!(DTSTDC, Z22), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_d0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x2_e0
        None, None, dfp25!(DTSTDG, Z22), dfpqa!(DRINTN, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_f0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x3_00
        None, None, dfp!(DRSP, X), dfpqa!(DQUA, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_10
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x3_20
        None, None, dfp27!(DCFFIX, X), dfpqa!(DRRND, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_30
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x3_40
        None, None, dfp!(DENBCD, X), dfpqa!(DQUAI, Z23), None, None, None, None,
        None, None, None, None, None, None, dfp26!(FCFIDS, X), None,
        // 0x3_50
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x3_60
        None, None, dfp!(DIEX, X), dfpqa!(DRINTX, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_70
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x3_80
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_90
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x3_a0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_b0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x3_c0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, dfp26!(FCFIDUS, X), None,
        // 0x3_d0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
        // 0x3_e0
        None, None, None, dfpqa!(DRINTN, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_f0
        None, None, opc!(FDIVS, A, FpuNoSingle), None, opc!(FSUBS, A, FpuNoSingle), opc!(FADDS, A, FpuNoSingle), opc!(FSQRTS, A, FpuNoSingle), None,
        opc!(FRES, A, FpuNoSingle), opc!(FMULS, A, FpuNoSingle), p203!(FRSQRTES, A), None, opc!(FMSUBS, A, FpuNoSingle), opc!(FMADDS, A, FpuNoSingle), opc!(FNMSUBS, A, FpuNoSingle), opc!(FNMADDS, A, FpuNoSingle),
    ]
};

static FP_DOUBLE_EXTENDED_OPS: ExtensionTable = ExtensionTable {
    bit_offset: 1,
    bit_count: 10,
    records: &[
        // 0x0_00
        opc!(FCMPU, X), None, dfp!(DADDQ, X), dfpqa!(DQUAQ, Z23), None, None, None, None,
        dfp!(FCPSGN, X), None, None, None, opc!(FRSP, X), None, opc!(FCTIW, X), opc!(FCTIWZ, X),
        // 0x0_10
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x0_20
        opc!(FCMPO, X), None, dfp!(DMULQ, X), dfpqa!(DRRNDQ, Z23), None, None, opc!(MTFSB1, X), None,
        opc!(FNEG, X), None, None, None, None, None, None, None,
        // 0x0_30
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x0_40
        opc!(MCRFS, X), None, dfp!(DSCLIQ, Z22), dfpqa!(DQUAIQ, Z23), None, None, opc!(MTFSB0, X), None,
        opc!(FMR, X, Fpu), None, None, None, None, None, None, None,
        // 0x0_50
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x0_60
        None, None, dfp!(DSCRIQ, Z22), dfpqa!(DRINTXQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_70
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x0_80
        p206!(FTDIV, X), None, dfp!(DCMPOQ, X), None, None, None, opc!(MTFSFI, X), None,
        opc!(FNABS, X), None, None, None, None, None, p206!(FCTIWU, X), p206!(FCTIWUZ, X),
        // 0x0_90
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x0_a0
        p206!(FTSQRT, X), None, dfp25!(DTSTEXQ, X), None, None, None, None, None,
        None, None, None, None, None, None, p206!(FCTIWU, X), p206!(FCTIWUZ, X),
        // 0x0_b0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x0_c0
        None, None, dfp25!(DTSTDCQ, Z22), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_d0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x0_e0
        None, None, dfp25!(DTSTDGQ, Z22), dfpqa!(DRINTNQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x0_f0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x1_00
        None, None, dfp!(DCTQPQ, X), dfpqa!(DQUAQ, Z23), None, None, None, None,
        opc!(FABS, X), None, None, None, None, None, None, None,
        // 0x1_10
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x1_20
        None, None, dfp!(DCTFIXQ, X), /* typo in Power ISA <3.0, "drrnd" */ dfpqa!(DRRNDQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_30
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x1_40
        None, None, dfp!(DDEDPDQ, X), dfpqa!(DQUAIQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_50
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x1_60
        None, None, dfp!(DXEXQ, X), dfpqa!(DRINTXQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x1_70
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x1_80
        None, None, None, None, None, None, None, None,
        p203!(FRIN, X), None, None, None, None, None, None, None,
        // 0x1_90
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x1_a0
        None, None, None, None, None, None, None, None,
        p203!(FRIZ, X), None, None, None, None, None, None, None,
        // 0x1_b0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x1_c0
        None, None, None, None, None, None, None, None,
        p203!(FRIP, X), None, None, None, None, None, None, None,
        // 0x1_d0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x1_e0
        None, None, None, dfpqa!(DRINTNQ, Z23), None, None, None, None,
        p203!(FRIM, X), None, None, None, None, None, None, None,
        // 0x1_f0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x2_00
        None, None, dfp!(DSUBQ, X), dfpqa!(DQUAQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_10
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x2_20
        None, None, dfp!(DDIVQ, X), /* typo in Power ISA <3.0, "drrnd" */ dfpqa!(DRRNDQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_30
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x2_40
        None, None, p206!(DSCLIQ, Z22), dfpqa!(DQUAIQ, Z23), None, None, None, opc!(MFFS, X),
        None, None, None, None, None, None, None, None,
        // 0x2_50
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x2_60
        None, None, p206!(DSCRIQ, Z22), dfpqa!(DRINTXQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_70
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x2_80
        None, None, dfp!(DCMPUQ, X), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_90
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x2_a0
        None, None, dfp25!(DTSTSFQ, X), None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_b0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x2_c0
        None, None, dfp25!(DTSTDCQ, Z22), None, None, None, None, opc!(MTFSF, XFL),
        None, None, None, None, None, None, None, None,
        // 0x2_d0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x2_e0
        None, None, dfp25!(DTSTDGQ, Z22), dfpqa!(DRINTNQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x2_f0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x3_00
        None, None, dfp!(DRDPQ, X), dfpqa!(DQUAQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_10
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x3_20
        None, None, dfp!(DCFFIXQ, X), /* typo in Power ISA <3.0, "drrnd" */ dfpqa!(DRRNDQ, Z23), None, None, None, None,
        None, None, None, None, None, None, opc!(FCTID, X), opc!(FCTIDZ, X),
        // 0x3_30
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x3_40
        None, None, dfp!(DENBCDQ, X), dfpqa!(DQUAIQ, Z23), None, None, None, None, // TODO: FMRGEW, vsx (book 2.07+)
        None, None, None, None, None, None, opc!(FCFID, X), None,
        // 0x3_50
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x3_60
        None, None, dfp!(DIEXQ, X), dfpqa!(DRINTXQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_70
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x3_80
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_90
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x3_a0
        None, None, None, None, None, None, None, None,
        None, None, None, None, None, None, p206!(FCTIDU, X), p206!(FCTIDUZ, X),
        // 0x3_b0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x3_c0
        None, None, None, None, None, None, None, None, // TODO: FMRGEW, vsx (book 2.07+)
        None, None, None, None, None, None, p206!(FCFIDU, X), None,
        // 0x3_d0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
        // 0x3_e0
        None, None, None, dfpqa!(DRINTNQ, Z23), None, None, None, None,
        None, None, None, None, None, None, None, None,
        // 0x3_f0
        None, None, opc!(FDIV, A, Fpu), None, opc!(FSUB, A, Fpu), opc!(FADD, A, Fpu), ppc!(FSQRT, A), ppc!(FSEL, A),
        p206!(FRE, A), opc!(FMUL, A, Fpu), ppc!(FRSQRTE, A), None, opc!(FMSUB, A, Fpu), opc!(FMADD, A, Fpu), opc!(FNMSUB, A, Fpu), opc!(FNMADD, A, Fpu),
    ],
};

const fn opc(op: Opcode, f: Format) -> PrimaryLookup {
    PrimaryLookup::Opc(op, f)
}

const fn opc_b(op: Opcode) -> PrimaryLookup {
    opc(op, Format::B)
}

const fn opc_d(op: Opcode) -> PrimaryLookup {
    opc(op, Format::D)
}

const fn opc_d_dot(op: Opcode) -> PrimaryLookup {
    opc(op, Format::Ddot)
}

const fn opc_d_mem(op: Opcode) -> PrimaryLookup {
    opc(op, Format::Dmem)
}

const fn opc_i(op: Opcode) -> PrimaryLookup {
    opc(op, Format::I)
}

const fn opc_m(op: Opcode) -> PrimaryLookup {
    opc(op, Format::M)
}

const fn opc_sc(op: Opcode) -> PrimaryLookup {
    opc(op, Format::SC)
}

impl InstDecoder {
    /// create a new `InstDecoder` for the provided `IsaVersion`.
    pub fn for_cpu(version: IsaVersion) -> Self {
        let mut this = Self::default();
        this.version = version;
        this
    }

    /// decode the provided slice into an instruction.
    ///
    /// if the slice is too short or does not describe a valid instruction, this will fail with
    /// `DecodeError`. this is a short-hand for using [`yaxpeax_arch::U8Reader`].
    pub fn decode_slice(&self, bytes: &[u8]) -> Result<Instruction, DecodeError> {
        let mut reader = yaxpeax_arch::U8Reader::new(bytes);
        self.decode(&mut reader)
    }

    fn decode_paired_single_opc4(&self, inst: &mut Instruction, word: u32) -> Result<(), <Power as Arch>::DecodeError> {
        let opc = (word >> 1) & 0x3ff;

        let rt = (word >> 21) & 0x1f;
        let ra = (word >> 16) & 0x1f;
        let rb = (word >> 11) & 0x1f;

        if opc == 0x3f6 {
            inst.opcode = Opcode::DCBZ_L;
            inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
            inst.operands[1] = Some(Operand::Register(Register { reg: rb as u8 }));
            return Ok(());
        }

        let opc_lo = opc & 0x1f;
        let opc_hi = (opc >> 5) & 0x1f;

        #[allow(non_camel_case_types)]
        #[derive(Copy, Clone, Debug)]
        enum OperandCode {
            TB,
            TAB,
            TAC,
            TACB,
            PS_LST,
        }

        fn read_ops(inst: &mut Instruction, code: OperandCode, word: u32) {
            let rt = (word >> 21) & 0x1f;
            let ra = (word >> 16) & 0x1f;
            let rb = (word >> 11) & 0x1f;
            let rc = (word >> 6) & 0x1f;
            let st = word & 1;

            match code {
                OperandCode::TB => {
                    inst.rc = st != 0;
                    inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                    inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                }
                OperandCode::TAB => {
                    inst.rc = st != 0;
                    inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                    inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                    inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                }
                OperandCode::TAC => {
                    inst.rc = st != 0;
                    inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                    inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                    inst.operands[2] = Some(Operand::FPR(FPR { reg: rc as u8 }));
                }
                OperandCode::TACB => {
                    inst.rc = st != 0;
                    inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                    inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                    inst.operands[2] = Some(Operand::FPR(FPR { reg: rc as u8 }));
                    inst.operands[3] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                }
                OperandCode::PS_LST => {
                    let w = (word >> 10) & 1;
                    let gqr = (word >> 7) & 0b111;
                    inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                    inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                    inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                    inst.operands[3] = Some(Operand::Imm8(w as u8));
                    inst.operands[4] = Some(Operand::GQR(GQR { reg: gqr as u8 }));
                }
            }
        }

        use OperandCode::*;

        static OPS: [Option<(Opcode, OperandCode)>; 32] = [
            None,                       None,                       None,                        None,
            None,                       None,                       None,                        None,
            None,                       None,                       Some((Opcode::PS_SUM0, TACB)),  Some((Opcode::PS_SUM1, TACB)),
            Some((Opcode::PS_MULS0, TAC)),Some((Opcode::PS_MULS1, TAC)),Some((Opcode::PS_MADDS0, TACB)),Some((Opcode::PS_MADDS1, TACB)),
            None,                       None,                       Some((Opcode::PS_DIV, TAB)),   None,
            Some((Opcode::PS_SUB, TAB)),Some((Opcode::PS_ADD, TAB)),None,                        Some((Opcode::PS_SEL, TACB)),
            Some((Opcode::PS_RES, TB)), Some((Opcode::PS_MUL, TAC)),Some((Opcode::PS_RSQRTE, TB)),None,
            Some((Opcode::PS_MSUB, TACB)), Some((Opcode::PS_MADD, TACB)), Some((Opcode::PS_NMSUB, TACB)), Some((Opcode::PS_NMADD, TACB)),
        ];

        if let Some((opc, oper_code)) = OPS[opc_lo as usize] {
            inst.opcode = opc;
            read_ops(inst, oper_code, word);
            Ok(())
        } else {
            if opc_lo == 0 {
                static OPS: [Opcode; 4] = [
                    Opcode::PS_CMPU0,
                    Opcode::PS_CMPO0,
                    Opcode::PS_CMPU1,
                    Opcode::PS_CMPO1,
                ];
                if opc_hi > 3 {
                    return Err(DecodeError::InvalidOpcode);
                }
                inst.opcode = OPS[opc_hi as usize & 0b11];
                inst.operands[0] = Some(Operand::CrField((rt as u8) >> 2));
                inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                Ok(())
            } else if opc_lo == 6 {
                inst.opcode = if opc_hi & 1 == 0 {
                    Opcode::PSQ_LX
                } else {
                    Opcode::PSQ_LUX
                };
                read_ops(inst, PS_LST, word);
                Ok(())
            } else if opc_lo == 7 {
                inst.opcode = if opc_hi & 1 == 0 {
                    Opcode::PSQ_STX
                } else {
                    Opcode::PSQ_STUX
                };
                read_ops(inst, PS_LST, word);
                Ok(())
            } else if opc_lo == 8 {
                inst.opcode = if opc_hi == 1 {
                    Opcode::PS_NEG
                } else if opc_hi == 2 {
                    Opcode::PS_MR
                } else if opc_hi == 4 {
                    Opcode::PS_NABS
                } else if opc_hi == 8 {
                    Opcode::PS_ABS
                } else {
                    return Err(DecodeError::InvalidOpcode);
                };
                read_ops(inst, TB, word);
                Ok(())
            } else if opc_lo == 16 {
                if opc_hi < 16 || opc_hi >= 20 {
                    return Err(DecodeError::InvalidOpcode);
                }
                static OPS: [Opcode; 4] = [
                    Opcode::PS_MERGE00,
                    Opcode::PS_MERGE01,
                    Opcode::PS_MERGE10,
                    Opcode::PS_MERGE11,
                ];
                inst.opcode = OPS[opc_hi as usize - 16];
                read_ops(inst, TAB, word);
                Ok(())
            } else {
                Err(DecodeError::InvalidOpcode)
            }
        }
    }

    fn decode_vmx128_opc4(&self, inst: &mut Instruction, word: u32) -> Result<(), <Power as Arch>::DecodeError> {
        let vdh = (word >> 2) & 0b11;
        let vd128 = (word >> 21) & 0b11111;
        let vd = vd128 | (vdh << 5);

        let opc_lo = (word >> 4) & 1;

        if opc_lo == 0 {
            let low_low = word & 0b110011;
            // std::eprintln!("low low: {:06b}", low_low);

            if low_low != 0b000011 {
                // and we're back to non-altivec!
                return self.decode_vector(inst, word);
            }
            let opc_mid = (word >> 5) & 1;
            if opc_mid != 0 {
                return Err(DecodeError::InvalidOpcode);
            }

            let ra = (word >> 16) & 0b11111;
            let rb = (word >> 11) & 0b11111;

            let opc_hi = (word >> 6) & 0x1f;
            static OPC4_VMX128: [Option<Opcode>; 32] = [
                Some(Opcode::LVSL128),  Some(Opcode::LVSR128),
                Some(Opcode::LVEWX128), Some(Opcode::LVX128),
                None,                   None,
                Some(Opcode::STVEWX128),Some(Opcode::STVX128),
                None,                   None,
                None,                   Some(Opcode::LVXL128),
                None                   ,None,
                None,                   Some(Opcode::STVXL128),
                Some(Opcode::LVLX128),  Some(Opcode::LVRX128),
                None,                   None,
                Some(Opcode::STVLX128), Some(Opcode::STVRX128),
                None, None,
                Some(Opcode::LVLXL128), Some(Opcode::LVRXL128),
                None,                   None,
                Some(Opcode::STVLXL128),Some(Opcode::STVRXL128),
                None,                   None,
            ];
            inst.opcode = OPC4_VMX128[opc_hi as usize].ok_or(DecodeError::InvalidOpcode)?;
            inst.operands[0] = Some(Operand::VR128(VR128 { reg: vd as u8 }));
            inst.operands[1] = Some(Operand::MemoryIndexed {
                base: Register { reg: ra as u8 },
                index: Register { reg: rb as u8 },
            });
        } else {
            inst.opcode = Opcode::VSLDOI128;

            let vdh = (word >> 2) & 0b11;
            let vd128 = (word >> 21) & 0b11111;
            let vd = vd128 | (vdh << 5);

            let vahh = (word >> 10) & 1;
            let vahl = (word >> 5) & 1;
            let vah = (vahh << 1) | vahl;
            let va128 = (word >> 16) & 0b11111;
            let va = va128 | (vah << 5);

            let vbh = (word >> 0) & 0b11;
            let vb128 = (word >> 11) & 0b11111;
            let vb = vb128 | (vbh << 5);

            inst.operands[0] = Some(Operand::VR128(VR128 { reg: vd as u8 }));
            inst.operands[1] = Some(Operand::VR128(VR128 { reg: va as u8 }));
            inst.operands[2] = Some(Operand::VR128(VR128 { reg: vb as u8 }));
            inst.operands[3] = Some(Operand::Imm8((word >> 6) as u8 & 0b1111));
        }

        Ok(())
    }

    fn decode_vmx128_opc5(&self, inst: &mut Instruction, word: u32) -> Result<(), <Power as Arch>::DecodeError> {
        let vdh = (word >> 2) & 0b11;
        let vd128 = (word >> 21) & 0b11111;
        let vd = vd128 | (vdh << 5);

        let vahh = (word >> 10) & 1;
        let vahl = (word >> 5) & 1;
        let vah = (vahh << 1) | vahl;
        let va128 = (word >> 16) & 0b11111;
        let va = va128 | (vah << 5);

        let vbh = (word >> 0) & 0b11;
        let vb128 = (word >> 11) & 0b11111;
        let vb = vb128 | (vbh << 5);

        inst.operands[0] = Some(Operand::VR128(VR128 { reg: vd as u8 }));
        inst.operands[1] = Some(Operand::VR128(VR128 { reg: va as u8 }));
        inst.operands[2] = Some(Operand::VR128(VR128 { reg: vb as u8 }));

        let opc_lo = (word >> 4) & 1;

        if opc_lo == 0 {
            let vc = (word >> 6) & 0b111;
            let opc_hi = (word >> 9) & 1;

            if opc_hi == 0 {
                inst.opcode = Opcode::VPERM128;
                inst.operands[3] = Some(Operand::VR128(VR128 { reg: vc as u8 }));
            } else {
                static OPS: [Opcode; 8] = [
                    Opcode::VPKSHSS128, Opcode::VPKSHUS128,
                    Opcode::VPKSWSS128, Opcode::VPKSWUS128,
                    Opcode::VPKUHUM128, Opcode::VPKUHUS128,
                    Opcode::VPKUWUM128, Opcode::VPKUWUS128,
                ];
                inst.opcode = OPS[vc as usize];
            }
        } else {
            let opc = (word >> 6) & 0b1111;
            static OPS: [Option<Opcode>; 16] = [
                Some(Opcode::VADDFP128), Some(Opcode::VSUBFP128),
                Some(Opcode::VMULFP128), Some(Opcode::VMADDFP128),
                Some(Opcode::VMADDCFP128), Some(Opcode::VNMSUBFP128),
                Some(Opcode::VMSUM3FP128), Some(Opcode::VMSUM4FP128),
                Some(Opcode::VAND128), Some(Opcode::VANDC128),
                Some(Opcode::VNOR128), Some(Opcode::VOR128),
                Some(Opcode::VXOR128), Some(Opcode::VSEL128),
                Some(Opcode::VSLO128), Some(Opcode::VSRO128),
            ];
            inst.opcode = OPS[opc as usize].ok_or(DecodeError::InvalidOpcode)?;
            if inst.opcode == Opcode::VMADDCFP128 || inst.opcode == Opcode::VNMSUBFP128 {
                inst.operands[3] = inst.operands[2];
                inst.operands[2] = inst.operands[0];
            } else if inst.opcode == Opcode::VMADDFP128 ||
                      inst.opcode == Opcode::VSEL128 {
                inst.operands[3] = inst.operands[0];
            }
        }

        Ok(())
    }

    fn decode_vmx128_opc6(&self, inst: &mut Instruction, word: u32) -> Result<(), <Power as Arch>::DecodeError> {
        // VMX128 uses opcode extension bits more aggressively than most other Power ISA bits, so
        // not as much of a table here..
        //
        // working heavily off of
        // https://github.com/xenia-project/xenia/blob/cc72de0/docs/ppc/vmx128.txt ...
        let opc_bit_low = (word >> 4) & 1;

        if opc_bit_low == 0 {
            // arguably the index is three bits at 7 and above
            let idx = (word >> 6) & 0b1111;

            let vbh = word & 0b11;
            let vdh = (word >> 2) & 0b11;
            let vb128 = (word >> 11) & 0b11111;
            let vd128 = (word >> 21) & 0b11111;

            let vd = vd128 | (vdh << 5);
            let vb = vb128 | (vbh << 5);

            inst.operands[0] = Some(Operand::VR128(VR128 { reg: vd as u8 }));

            if idx >= 0b1110 {
                inst.operands[1] = Some(Operand::VR128(VR128 { reg: vb as u8 }));
                if idx == 0b1110 {
                    inst.opcode = Opcode::VUPKHSB128;
                } else /* idx == 0b1111 */ {
                    inst.opcode = Opcode::VUPKLSB128;
                }

                if word & 0b000000_00000_11111_00000_1000010_00_00 != 0 {
                    // xenia documents this as VA128==0/VAh==0, but decodes as these unpack
                    // instructions regardless of the bits that are present. HELP: not sure what
                    // hardware tolerates.
                    // return Err(DecodeError::InvalidOperand);
                }
            } else {
                let va128 = (word >> 16) & 0b11111;
                let vahh = (word >> 10) & 1;
                let vahl = (word >> 5) & 1;
                let vah = (vahh << 1) | vahl;
                let va = va128 | (vah << 5);
                inst.operands[1] = Some(Operand::VR128(VR128 { reg: va as u8 }));
                inst.operands[2] = Some(Operand::VR128(VR128 { reg: vb as u8 }));

                static OPCS: [Opcode; 14] = [
                    Opcode::VCMPEQFP128,  Opcode::VCMPEQFP128,
                    Opcode::VCMPGEFP128,  Opcode::VCMPGEFP128,
                    Opcode::VCMPGTFP128,  Opcode::VCMPGTFP128,
                    Opcode::VCMPBFP128,   Opcode::VCMPBFP128,
                    Opcode::VCMPEQUW128,  Opcode::VCMPEQUW128,
                    Opcode::VMAXFP128,    Opcode::VMINFP128,
                    Opcode::VMRGHW128,    Opcode::VMRGLW128,
                ];
                inst.opcode = OPCS[idx as usize];
                if idx <= 0b1010 {
                    let r = (word >> 6) & 1;
                    inst.rc = r != 0;
                }
            }
            Ok(())
        } else {
            // you'll want altivec_instructions_reordered.txt handy and tuned to instructions
            // starting with `0 0 0 1 1 0` for this next bit.

            let vb128 = (word >> 11) & 0b11111;
            let va128 = (word >> 16) & 0b11111;
            let vd128 = (word >> 21) & 0b11111;

            let vbh = word & 0b11;
            let vdh = (word >> 2) & 0b11;
            let vahh = (word >> 10) & 1;
            let vahl = (word >> 5) & 1;
            let vah = (vahh << 1) | vahl;

            let vd = (vdh << 5) | vd128;
            let vb = (vbh << 5) | vb128;
            let va = (vah << 5) | va128;

            inst.operands[0] = Some(Operand::VR128(VR128 { reg: vd as u8 }));
            inst.operands[1] = Some(Operand::VR128(VR128 { reg: vb as u8 }));

            let opc_hi = (word >> 9) & 1;

            if opc_hi == 0 {
                let opc_lo = (word >> 6) & 0b111;
                inst.operands[1] = Some(Operand::VR128(VR128 { reg: va as u8 }));
                inst.operands[2] = Some(Operand::VR128(VR128 { reg: vb as u8 }));
                static SHIFT_OPS: [Option<Opcode>; 8] = [
                    None, Some(Opcode::VRLW128), None, Some(Opcode::VSLW128),
                    None, Some(Opcode::VSRAW128), None, Some(Opcode::VSRW128),
                ];
                inst.opcode = SHIFT_OPS[opc_lo as usize].ok_or(DecodeError::InvalidOpcode)?;
                return Ok(());
            }

            if (word >> 5) & 1 == 0 {

                if (word >> 10) & 1 == 0 {
                    inst.opcode = Opcode::VPERMWI128;
                    let perml = (word >> 16) & 0b11111;
                    let permh = (word >> 6) & 0b111;
                    let perm = (permh << 5) | perml;

                    inst.operands[2] = Some(Operand::Imm8(perm as u8));

                } else {
                    // vpkd3d128 or vrlimi128, depending on ..
                    let z = (word >> 6) & 0b11;
                    if (word >> 8) & 1 == 0 {
                        let x = (va128 >> 2) as u8;
                        let y = va128 & 0b11;

                        inst.opcode = Opcode::VPKD3D128;
                        inst.operands[2] = Some(
                            Operand::PixelFormat(PixelFormat::from_u8(x))
                        );
                        inst.operands[3] = Some(Operand::Imm8(y as u8));
                        inst.operands[4] = Some(Operand::Imm8(z as u8));
                    } else {
                        inst.opcode = Opcode::VRLIMI128;
                        inst.operands[2] = Some(Operand::Imm8(va128 as u8));
                        inst.operands[3] = Some(Operand::Imm8(z as u8));
                    }
                }
                return Ok(());
            }

            // we've ruled out bits 4, 5, and 9 for choosing the opcode at this point.
            // that leaves bits 6, 7, 8, and 10. we'll collect them in a funny way, but it'll do..

            let opc_bits = (word >> 6) & 0b1_1111;
            let idx = (opc_bits & 0b111) | ((opc_bits >> 1) & 0b1_000);

            static OPCODES: [Option<Opcode>; 16] = [
                Some(Opcode::VCFPSXWS128),
                Some(Opcode::VCFPUXWS128),
                Some(Opcode::VCSXWFP128),
                Some(Opcode::VCUXWFP128),
                Some(Opcode::VRFIM128),
                Some(Opcode::VRFIN128),
                Some(Opcode::VRFIP128),
                Some(Opcode::VRFIZ128),

                Some(Opcode::VREFP128),
                Some(Opcode::VRSQRTEFP128),
                Some(Opcode::VEXPTEFP128),
                Some(Opcode::VLOGEFP128),
                Some(Opcode::VSPLTW128),
                Some(Opcode::VSPLTISW128),
                None,
                Some(Opcode::VUPKD3D128),
            ];

            inst.opcode = OPCODES[idx as usize].ok_or(DecodeError::InvalidOpcode)?;

            if idx < 4 || idx >= 12  {
                if inst.opcode == Opcode::VSPLTISW128 {
                    let extended = ((va128 << 3) as i8) >> 3;
                    inst.operands[1] = Some(Operand::ImmExts16(extended as i16));
                } else if inst.opcode == Opcode::VUPKD3D128 {
                    let x = (va128 >> 2) as u8;
                    inst.operands[2] = Some(
                        Operand::PixelFormat(PixelFormat::from_u8(x))
                    );
                } else {
                    inst.operands[2] = Some(Operand::Imm8(va128 as u8));
                }
            }

            Ok(())
        }
    }

    fn decode_vector(&self, inst: &mut Instruction, word: u32) -> Result<(), <Power as Arch>::DecodeError> {
        let table = VECTOR_LMA;

        assert!(table.bit_count != 0);
        let idx = table.extract_idx(word);

        let table_section = (idx >> 4) & 0b11;
        let opc_idx = idx & 0b1111;
        let _row = idx >> 6;
        // std::eprintln!("table/opc: {:02b}, opc={}, row={:05b}", table_section, opc_idx, row);

        if table_section == 0b10 {
            // as of Power v2.06, this section is best described under:
            // > Table 8 (Right-Center) Extended opcodes for primary opcode 4 [Categroy: V & LMA]
            static LMA: [Option<Opcode>; 16] = [
                Some(Opcode::VMHADDSHS), Some(Opcode::VMHRADDSHS), Some(Opcode::VMLADDUHM), None,
                Some(Opcode::VMSUMUBM), Some(Opcode::VMSUMMBM), Some(Opcode::VMSUMUHM), Some(Opcode::VMSUMUHS),
                Some(Opcode::VMSUMSHM), Some(Opcode::VMSUMSHS), Some(Opcode::VSEL), Some(Opcode::VPERM),
                Some(Opcode::VSLDOI), None, Some(Opcode::VMADDFP), Some(Opcode::VNMSUBFP),
            ];
            inst.opcode = LMA[opc_idx as usize].ok_or(DecodeError::InvalidOpcode)?;

            let rc = ((word >> 6) & 0b11111) as u8;
            let rb = ((word >> 11) & 0b11111) as u8;
            let ra = ((word >> 16) & 0b11111) as u8;
            let rt = ((word >> 21) & 0b11111) as u8;

            inst.operands[0] = Some(Operand::VR(VR { reg: rt }));

            if inst.opcode == Opcode::VSEL || inst.opcode == Opcode::VPERM {
                inst.operands[1] = Some(Operand::VR(VR { reg: ra }));
                inst.operands[2] = Some(Operand::VR(VR { reg: rb }));
                inst.operands[3] = Some(Operand::VR(VR { reg: rc }));
            } else if inst.opcode == Opcode::VMADDFP || inst.opcode == Opcode::VNMSUBFP {
                inst.operands[1] = Some(Operand::VR(VR { reg: ra }));
                inst.operands[2] = Some(Operand::VR(VR { reg: rc }));
                inst.operands[3] = Some(Operand::VR(VR { reg: rb }));
            } else if inst.opcode == Opcode::VSLDOI {
                inst.operands[1] = Some(Operand::VR(VR { reg: ra }));
                inst.operands[2] = Some(Operand::VR(VR { reg: rb }));
                inst.operands[3] = Some(Operand::Imm8(rc & 0b1111));
            } else {
                inst.operands[1] = Some(Operand::VR(VR { reg: ra }));
                inst.operands[2] = Some(Operand::VR(VR { reg: rb }));
                inst.operands[3] = Some(Operand::VR(VR { reg: rc }));
            }
            return Ok(());
        } else if table_section == 0b11 {
            // as of Power v2.06, this section is zero:
            // > Table 8 (Right) Extended opcodes for primary opcode 4
            //
            // starting in v2.07, and more in v3.00, instructions become defined in this section.
            if self.version.supports(IsaConstraint::PowerIsa207) {
                // TODO:
                return Err(DecodeError::IncompleteDecoder);
            }

            // panic!("table section {:02b}, idx {:#x}", table_section, opc_idx);
            return Err(DecodeError::InvalidOpcode);
        }

        if opc_idx & 1 != 0 {
            // as of at least Power v2.07, no LMA-table entry had a low bit set in the opcode.
            return Err(DecodeError::InvalidOpcode);
        }

        let compressed_idx = (opc_idx >> 1) | ((idx >> 6) << 4);

        // the remaining parts of `table_section == 0b00 or 0b01`. the low bit is compressed out,
        // and the high bit of table section is compressed out, so only 9 bits are needed to index
        // the table.
        match table.records[compressed_idx] {
            Some(OpcodeRecord { lookup, isa_constraint, category: _ }) => {
                if !self.version.supports(isa_constraint) {
                    // std::eprintln!("bailing because {:?} does not support {:?}", self.version, isa_constraint);
                    return Err(DecodeError::InvalidOpcode);
                }
                // std::eprintln!("{:?} supports {:?}", self.version, isa_constraint);
                match lookup {
                    PrimaryLookup::Opc(opc, format) => {
                        inst.opcode = opc;
                        match format {
                            Format::VC => {
                                let rb = (word >> 11) & 0b11111;
                                let ra = (word >> 16) & 0b11111;
                                let rt = (word >> 21) & 0b11111;
                                inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                                inst.operands[1] = Some(Operand::VR(VR { reg: ra as u8 }));
                                inst.operands[2] = Some(Operand::VR(VR { reg: rb as u8 }));
                            }
                            Format::VCdot => {
                                inst.rc = true;
                                let rb = (word >> 11) & 0b11111;
                                let ra = (word >> 16) & 0b11111;
                                let rt = (word >> 21) & 0b11111;
                                inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                                inst.operands[1] = Some(Operand::VR(VR { reg: ra as u8 }));
                                inst.operands[2] = Some(Operand::VR(VR { reg: rb as u8 }));
                            }
                            Format::VX => {
                                static TWO_REGS: &'static [Opcode] = &[
                                    Opcode::VUPKHPX, Opcode::VUPKHSB,
                                    Opcode::VUPKHSH, Opcode::VUPKLPX,
                                    Opcode::VUPKLSB, Opcode::VUPKLSH,
                                    Opcode::VRFIM, Opcode::VRFIN,
                                    Opcode::VRFIP, Opcode::VRFIZ,
                                    Opcode::VEXPTEFP, Opcode::VLOGEFP,
                                    Opcode::VREFP, Opcode::VRSQRTEFP,
                                ];

                                let rb = (word >> 11) & 0b11111;
                                let ra = (word >> 16) & 0b11111;
                                let rt = (word >> 21) & 0b11111;
                                inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                                if TWO_REGS.contains(&opc) {
                                    inst.operands[1] = Some(Operand::VR(VR { reg: rb as u8 }));
                                } else {
                                    if opc == Opcode::VSPLTB {
                                        inst.operands[1] = Some(Operand::VR(VR { reg: rb as u8 }));
                                        inst.operands[2] = Some(Operand::Imm8(ra as u8 & 0b1111));
                                    } else if opc == Opcode::VSPLTISW ||
                                        opc == Opcode::VSPLTISH ||
                                        opc == Opcode::VSPLTISB {
                                        // `SIM` is sign-extended to the opcode's selected lane width
                                        let sim = ((ra << 3) as i8) >> 3;
                                        inst.operands[1] = Some(Operand::ImmExts16(sim as i16));
                                    } else if opc == Opcode::VSPLTH {
                                        inst.operands[1] = Some(Operand::VR(VR { reg: rb as u8 }));
                                        inst.operands[2] = Some(Operand::Imm8(ra as u8 & 0b111));
                                    } else if opc == Opcode::VSPLTW {
                                        inst.operands[1] = Some(Operand::VR(VR { reg: rb as u8 }));
                                        inst.operands[2] = Some(Operand::Imm8(ra as u8 & 0b11));
                                    } else if opc == Opcode::VCTSXS || opc == Opcode::VCTUXS ||
                                              opc == Opcode::VCFSX  || opc == Opcode::VCFUX {
                                        inst.operands[1] = Some(Operand::VR(VR { reg: rb as u8 }));
                                        inst.operands[2] = Some(Operand::Imm8(ra as u8));
                                    } else if opc == Opcode::MTVSCR {
                                        inst.operands[0] = Some(Operand::VR(VR { reg: rb as u8 }));
                                    } else if opc == Opcode::VCFUX || opc == Opcode::MFVSCR {
                                    } else {
                                        inst.operands[1] = Some(Operand::VR(VR { reg: ra as u8 }));
                                        inst.operands[2] = Some(Operand::VR(VR { reg: rb as u8 }));
                                    }
                                }
                            }
                            other => {
                                panic!("unhandled vsx instruction format {:?}", other);
                            }
                        }
                        Ok(())
                    }
                    other => {
                        panic!("other: {:?}", other);
                    }
                }
            }
            None => {
                // TODO:
                // panic!("table section {:02b}, idx {:#x}", table_section, compressed_idx);
                // std::eprintln!("table section {:02b}, idx {:#x}", table_section, compressed_idx);
                Err(DecodeError::InvalidOpcode)
            }
        }
    }
}

// TODO: v2.03 mentions Variable Length Encoding as 16-up-to-32-bit encoding that mandates
// big-endian instruction pages
// > defines alternative instruction encodings and definitions intended to increase instruction
// > density for very low end implementations. It was derived from an APU description developed by
// > Freescale Semiconductor.
#[allow(non_snake_case)]
impl Decoder<Power> for InstDecoder {
    fn decode_into<T: Reader<<Power as Arch>::Address, <Power as Arch>::Word>>(&self, inst: &mut Instruction, words: &mut T) -> Result<(), <Power as Arch>::DecodeError> {
        inst.opcode = Opcode::XORI;
        inst.operands = [None; 5];
        inst.rc = false;
        inst.lk = false;
        inst.aa = false;
        inst.oe = false;

        let word = words.next()?;

        let mut word = word.0;

        if !self.is_be {
            word = word.swap_bytes();
        }

        // TODO: handling for compressed encodings
        inst.len = 4;

        let opc = word >> 26;

        const fn undef() -> PrimaryLookup {
            PrimaryLookup::Undefined
        }

        /// taken from PowerISA V2.03 Appendix F "Opcode Maps", table 1:
        static OP_LUT: [PrimaryLookup; 64] = [
            // opc: 00
            PrimaryLookup::ImplementationDefined, undef(), opc_d(Opcode::TDI), opc_d(Opcode::TWI),
            PrimaryLookup::Opc4, PrimaryLookup::Opc5, PrimaryLookup::Opc6, opc_d(Opcode::MULLI),
            // opc: 08
            opc_d(Opcode::SUBFIC), opc_d(Opcode::DOZI), opc_d(Opcode::CMPLI), opc_d(Opcode::CMPI),
            opc_d(Opcode::ADDIC), opc_d_dot(Opcode::ADDIC), opc_d(Opcode::ADDI), opc_d(Opcode::ADDIS),
            // opc: 10
            opc_b(Opcode::BC), opc_sc(Opcode::SC), opc_i(Opcode::B), PrimaryLookup::Extension(&CR_OPS),
            opc_m(Opcode::RLWIMI), opc_m(Opcode::RLWINM), PrimaryLookup::Opc(Opcode::RLMI, Format::X), opc_m(Opcode::RLWNM),
            // opc: 18
            opc_d(Opcode::ORI), opc_d(Opcode::ORIS), opc_d(Opcode::XORI), opc_d(Opcode::XORIS),
            opc_d_dot(Opcode::ANDI), opc_d_dot(Opcode::ANDIS), PrimaryLookup::Extension(&FX_DWD_ROT), PrimaryLookup::Extension(&FX_EXTENDED_OPS),
            // opc: 20
            opc_d_mem(Opcode::LWZ), opc_d_mem(Opcode::LWZU), opc_d_mem(Opcode::LBZ), opc_d_mem(Opcode::LBZU),
            opc_d_mem(Opcode::STW), opc_d_mem(Opcode::STWU), opc_d_mem(Opcode::STB), opc_d_mem(Opcode::STBU),
            // opc: 28
            opc_d_mem(Opcode::LHZ), opc_d_mem(Opcode::LHZU), opc_d_mem(Opcode::LHA), opc_d_mem(Opcode::LHAU),
            opc_d_mem(Opcode::STH), opc_d_mem(Opcode::STHU), opc_d_mem(Opcode::LMW), opc_d_mem(Opcode::STMW),
            // opc: 30
            opc_d_mem(Opcode::LFS), opc_d_mem(Opcode::LFSU), opc_d_mem(Opcode::LFD), opc_d_mem(Opcode::LFDU),
            opc_d_mem(Opcode::STFS), opc_d_mem(Opcode::STFSU), opc_d_mem(Opcode::STFD), opc_d_mem(Opcode::STFDU),
            // opc: 38
            PrimaryLookup::Opc38, PrimaryLookup::Opc39, PrimaryLookup::Extension(&FX_DS_LOADS), PrimaryLookup::Extension(&FP_SINGLE_EXTENDED_OPS),
            PrimaryLookup::Opc3C, PrimaryLookup::Opc3D, PrimaryLookup::Extension(&FX_DS_STORES), PrimaryLookup::Extension(&FP_DOUBLE_EXTENDED_OPS),
        ];

        let (opc, enc) = match OP_LUT[opc as usize] {
            PrimaryLookup::ImplementationDefined => {
                let mut decoded = false;
                if self.version == IsaVersion::A2 || self.version == IsaVersion::All {
                    let xo = (word >> 1) & 0x3_ff;
                    if xo == 256 {
                        inst.opcode = Opcode::ATTN;
                        decoded = true;
                    }
                }
                if decoded {
                    return Ok(());
                }
                return Err(DecodeError::IncompleteDecoder);
            }
            PrimaryLookup::Opc4 => {
                // TODO: require the selected isa version to include Vector (or SPE)
                // std::eprintln!("decode mode: {:?}", self.opc4_mode());
                match self.opc4_mode() {
                    Some(Opc4Mode::SP) => {
                        panic!("incomplete: SP.*");
                    }
                    Some(Opc4Mode::AltiVec) | Some(Opc4Mode::VSX) => {
                        return self.decode_vector(inst, word);
                    }
                    Some(Opc4Mode::VMX128) => {
                        return self.decode_vmx128_opc4(inst, word);
                    }
                    Some(Opc4Mode::PS) => {
                        return self.decode_paired_single_opc4(inst, word);
                    }
                    None => {
                        return Err(DecodeError::InvalidOpcode);
                    }
                }
            }
            PrimaryLookup::Opc5 => {
                if self.version.supports(IsaConstraint::VMX128) {
                    return self.decode_vmx128_opc5(inst, word);
                } else {
                    return Err(DecodeError::InvalidOpcode);
                }
            }
            PrimaryLookup::Opc6 => {
                if self.version.supports(IsaConstraint::VMX128) {
                    return self.decode_vmx128_opc6(inst, word);
                } else {
                    return Err(DecodeError::InvalidOpcode);
                }
            }
            PrimaryLookup::Illegal |
            PrimaryLookup::Undefined => {
                return Err(DecodeError::InvalidOpcode);
            }
            PrimaryLookup::Extension(table) => {
                if table.bit_count == 0 {
                    panic!("unimplemented table: opcode {}", opc);
                }
                let idx = table.extract_idx(word);

                match table.records[idx] {
                    Some(record) => {
                        if !self.version.supports(record.isa_constraint) {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        match record.lookup {
                            PrimaryLookup::Opc(opc, enc) => {
                                (opc, enc)
                            }
                            PrimaryLookup::Illegal => {
                                return Err(DecodeError::InvalidOpcode);
                            },
                            PrimaryLookup::Undefined => {
                                return Err(DecodeError::InvalidOpcode);
                            },
                            PrimaryLookup::Extension(_) => {
                                panic!("primary extension -> primary extension? {:x}", idx);
                            },
                            PrimaryLookup::ImplementationDefined => {
                                panic!("implementation defined?!");
                            }
                            PrimaryLookup::Opc4 | PrimaryLookup::Opc5 | PrimaryLookup::Opc6 |
                            PrimaryLookup::Opc38 | PrimaryLookup::Opc39 | PrimaryLookup::Opc3C | PrimaryLookup::Opc3D => {
                                panic!("TODO: impossible");
                            }
                        }
                    },
                    None => {
//                        panic!("no record for primary {:02x}/secondary {:03x}", opc, idx);
                        return Err(DecodeError::InvalidOpcode);
                    }
                }
            }
            PrimaryLookup::Opc38 => {
                // lfq is generally much more likely to be what someone expects to decode, but if
                // you're gekko then you get psq_l!
                if self.version == IsaVersion::All || !self.version.supports(IsaConstraint::Gekko) {
                    (Opcode::LFQ, Format::Dmem)
                } else {
                    (Opcode::PSQ_L, Format::PS_LST)
                }
            }
            PrimaryLookup::Opc39 => {
                match self.opc39_mode() {
                    Some(Opc39Mode::Gekko) => {
                        (Opcode::PSQ_LU, Format::PS_LST)
                    }
                    Some(Opc39Mode::POWER2) => {
                        (Opcode::LFQU, Format::DS)
                    }
                    Some(Opc39Mode::DFP) => {
                        (Opcode::LFDP, Format::DS)
                    }
                    None => {
                        return Err(DecodeError::InvalidOpcode);
                    }
                }
            }
            PrimaryLookup::Opc3C => {
                match self.opc3c_mode() {
                    Some(Opc3cMode::Gekko) => {
                        (Opcode::PSQ_ST, Format::PS_LST)
                    }
                    Some(Opc3cMode::POWER2) => {
                        (Opcode::STFQ, Format::DS)
                    }
                    Some(Opc3cMode::VSX) => {
                        // under VSX (in 2.07 and later) opcode 60 is used for an extension table.
                        // see:
                        // > Table 23: EXT60: Extended Opcode Map for Primary Opcode 60
                        return Err(DecodeError::IncompleteDecoder);
                    }
                    None => {
                        return Err(DecodeError::InvalidOpcode);
                    }
                }
            }
            PrimaryLookup::Opc3D => {
                match self.opc3d_mode() {
                    Some(Opc3dMode::Gekko) => {
                        (Opcode::PSQ_STU, Format::PS_LST)
                    }
                    Some(Opc3dMode::POWER2) => {
                        (Opcode::STFQU, Format::DS)
                    }
                    Some(Opc3dMode::STFDP) => {
                        (Opcode::STFDP, Format::X)
                    }
                    Some(Opc3dMode::VSX) => {
                        // in 2.05 and later
                        // > Table 14: EXT61: Extended Opcode Map for Primary Opcode 61
                        // but at least for xo=00 we can still say stfdp..
                        if word & 0b11 == 0b00 {
                            (Opcode::STFDP, Format::X)
                        } else {
                            return Err(DecodeError::IncompleteDecoder);
                        }
                    }
                    None => {
                        return Err(DecodeError::InvalidOpcode);
                    }
                }
            }
            PrimaryLookup::Opc(opc, enc) => {
                if opc == Opcode::TDI && !self.version.supports(IsaConstraint::Ppc64) {
                    // it's a bit difficult to fit this one-off constraint in the table above, so
                    // for now it's only checked later, at this point..
                    return Err(DecodeError::InvalidOpcode);
                }
                (opc, enc)
            }
        };

        inst.opcode = opc;

        match enc {
            Format::A => {
                let rt = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let rb = (word >> 11) & 0x1f;
                let rc = (word >> 6) & 0x1f;
                let lk = word & 1;

                inst.rc = lk != 0;

                match inst.opcode {
                    Opcode::ISEL => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::RegisterOrZero(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                        inst.operands[3] = Some(Operand::CrBit(rc as u8));
                        // `isel` specifically ignores Rc
                        inst.rc = false;
                    }
                    Opcode::FRE | Opcode::FRES => {
                        // TODO: not sure when `fre`/`fres` were added. as of 2.03 these are
                        // "phased-in". what CPU first supported them?

                        if self.version.supports(IsaConstraint::Ppc) {
                            inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                            inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        } else {
                            return Err(DecodeError::InvalidOpcode);
                        }
                    }
                    Opcode::FSQRT | Opcode::FSQRTS | Opcode::FRSQRTE | Opcode::FRSQRTES => {
                        // TODO: this probably should be an fsqrt isa constraint that gekko does
                        // not support, rather than .. this
                        if self.version == IsaVersion::Gekko {
                            if inst.opcode == Opcode::FSQRT || inst.opcode == Opcode::FSQRTS {
                                return Err(DecodeError::InvalidOpcode);
                            }
                        } else if !self.version.supports(IsaConstraint::Fpu) {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                    }
                    Opcode::FADD | Opcode::FADDS |
                    Opcode::FSUB | Opcode::FSUBS |
                    Opcode::FDIV | Opcode::FDIVS => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                    }
                    Opcode::FMUL | Opcode::FMULS => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rc as u8 }));
                    }
                    Opcode::FMADD | Opcode::FMSUB |
                    Opcode::FMADDS | Opcode::FMSUBS |
                    Opcode::FNMADD | Opcode::FNMSUB |
                    Opcode::FNMADDS | Opcode::FNMSUBS |
                    Opcode::FSEL  => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rc as u8 }));
                        inst.operands[3] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                    }
                    _ => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                }
            }
            Format::I => {
                let li = (word >> 2) & 0xff_ff_ff;
                let aa = (word >> 1) & 1;
                let lk = word & 1;

                inst.aa = aa != 0;
                inst.lk = lk != 0;

                assert_eq!(inst.opcode, Opcode::B);

                let extended = ((li << 8) as i32) >> 6;

                inst.opcode = if aa == 0 {
                    inst.operands[0] = Some(Operand::BranchOffset(extended as i32));
                    if lk == 0 {
                        Opcode::B
                    } else {
                        Opcode::BL
                    }
                } else {
                    inst.operands[0] = Some(Operand::BranchAbs(extended as i32));
                    if lk == 0 {
                        Opcode::BA
                    } else {
                        Opcode::BLA
                    }
                }
            }
            Format::B => {
                let bo = (word >> 21) & 0x1f;
                let bi = (word >> 16) & 0x1f;
                let bd = (word >> 2) & 0x3f_ff;
                let aa = (word >> 1) & 1;
                let lk = word & 1;

                inst.aa = aa != 0;
                inst.lk = lk != 0;

                inst.operands[0] = Some(Operand::Imm8(bo as u8));
                inst.operands[1] = Some(Operand::CrBit(bi as u8));

                if aa == 0 {
                    inst.operands[2] = Some(Operand::BranchOffset16((bd << 2) as i16));
                } else {
                    inst.operands[2] = Some(Operand::BranchAbs((bd << 2) as i16 as i32));
                };

                inst.opcode = if inst.aa {
                    if inst.lk {
                        Opcode::BCLA
                    } else {
                        Opcode::BCA
                    }
                } else {
                    if inst.lk {
                        Opcode::BCL
                    } else {
                        Opcode::BC
                    }
                };

                if self.version == IsaVersion::RIOS || self.version == IsaVersion::RIOS2 {
                    inst.hint_style = None;
                } else if !self.version.supports(IsaConstraint::PowerIsa200) || self.version == IsaVersion::e500 {
                    inst.hint_style = Some(HintStyle::Legacy);
                } else {
                    inst.hint_style = Some(HintStyle::PowerIsa);
                }
            }
            Format::SC => {
                let lev = (word >> 5) & 0x7f;
                let aa = (word >> 1) & 1;

                if self.version == IsaVersion::RIOS || self.version == IsaVersion::RIOS2 {
                    // in the *old* days, POWER1 and POWER2, what is now `sc` was instead `svc` for
                    // `supervisor call`, and had slightly different interpretation..
                    // HELP: i would love a POWER1/POWER2 referece. this is reverse engineered out
                    // of the AIX 5.3 assembler reference, lacking those.
                    inst.opcode = Opcode::SVC;
                    let lk = word & 1;
                    inst.lk = lk != 0;
                    inst.aa = aa != 0;

                    if aa == 1 {
                        // svca, which has different operands!
                        let sv = (word >> 2) & 0x3f_ff;
                        inst.operands[0] = Some(Operand::ImmU16(sv as u16));
                    } else {
                        // svc or svcl
                        let fl1 = (word >> 12) & 0xf;
                        let fl2 = (word >> 2) & 0x7;
                        inst.operands[0] = Some(Operand::ImmU16(lev as u16));
                        inst.operands[1] = Some(Operand::Imm8(fl1 as u8));
                        inst.operands[2] = Some(Operand::Imm8(fl2 as u8));
                    }

                    return Ok(());
                }

                if aa != 1 {
                    // SC-form mandates bit 30 is set at least in 2.03+..
                    // except Xenia doesn't require aa=1.. what does hardware want?
                    //
                    // ppcd is super strict about should-be-zero/must-be-zero, gekko may actually
                    // reject this.
                    if !self.version.supports(IsaConstraint::Xenon) && self.version != IsaVersion::Gekko {
                        return Err(DecodeError::InvalidOperand);
                    }
                }

                // > The use of the LEV field is described in Book III. The
                // > LEV values greater than 1 are reserved, and bits 0:5 of
                // > the LEV field (instruction bits 20:25) are treated as a
                // > reserved field.
                // TODO: error(?) if lev > 1
                inst.operands[0] = Some(Operand::Imm8(lev as u8));
            }
            // the specific form of some D-form instructions that have the semantic of the rc bit
            // being set.
            Format::Ddot => {
                let rt = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let si = word & 0xffff;

                inst.rc = true;

                match inst.opcode {
                    Opcode::ANDI | Opcode::ANDIS => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::ImmU16(si as u16));
                    }
                    _ => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::ImmExts16(si as i16));
                    }
                }
            }
            Format::D => {
                let rt = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let si = word & 0xffff;

                match opc {
                    Opcode::CMPI => {
                        let bf = rt >> 2;
                        let l = rt & 1;
                        if l == 1 && !self.version.supports(IsaConstraint::Ppc64) {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.operands[0] = Some(Operand::CrField(bf as u8));
                        inst.operands[1] = Some(Operand::Imm8(l as u8));
                        inst.operands[2] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[3] = Some(Operand::ImmExts16(si as i16));
                    }
                    Opcode::CMPLI => {
                        let bf = rt >> 2;
                        let l = rt & 1;
                        // the L bit is only respected where 64b *could* have existed, which is to
                        // say "after POWER2"..
                        if self.version != IsaVersion::RIOS && self.version != IsaVersion::RIOS2 {
                            if l == 1 && !self.version.supports(IsaConstraint::Ppc64) {
                                return Err(DecodeError::InvalidOpcode);
                            }
                        }
                        inst.operands[0] = Some(Operand::CrField(bf as u8));
                        inst.operands[1] = Some(Operand::Imm8(l as u8));
                        inst.operands[2] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[3] = Some(Operand::ImmU16(si as u16));
                    }
                    Opcode::TDI | Opcode::TWI => {
                        inst.operands[0] = Some(Operand::Imm8(rt as u8));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::ImmExts16(si as i16));
                    }
                    Opcode::ADDI | Opcode::ADDIS => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::RegisterOrZero(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::ImmExts16(si as i16));
                    }
                    Opcode::ADDIC | Opcode::SUBFIC | Opcode::MULLI => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::ImmExts16(si as i16));
                    }
                    // some D-form instructions have unsigned immediates instead
                    Opcode::ORI | Opcode::ORIS |
                    Opcode::XORI | Opcode::XORIS => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::ImmU16(si as u16));
                    }
                    Opcode::DOZI => {
                        if !self.version.supports(IsaConstraint::LE_POWER2) {
                            return Err(DecodeError::InvalidOpcode);
                        }

                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::ImmExts16(si as i16));
                    }
                    _ => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::ImmExts16(si as i16));
                    }
                }
            }
            Format::Dmem => {
                let rt = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let si = word & 0xffff;

                match inst.opcode {
                    Opcode::LFS | Opcode::LFD | Opcode::LFSU | Opcode::LFDU |
                    Opcode::STFS | Opcode::STFD | Opcode::STFSU | Opcode::STFDU => {
                        if !self.version.supports(IsaConstraint::Fpu) {
                            return Err(DecodeError::InvalidOpcode);
                        }

                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                    },
                    Opcode::LFQ => {
                        if !self.version.supports(IsaConstraint::LE_POWER2) {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        if !self.version.supports(IsaConstraint::Fpu) {
                            return Err(DecodeError::InvalidOpcode);
                        }

                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                    },
                    _ => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                    }
                }
                inst.operands[1] = Some(Operand::MemoryDisp { base: Register { reg: ra as u8 }, disp: si as i16 });
            }
            Format::DS => {
                let rt = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let ds = (word >> 2) & 0x3fff;
                // for some of these, like `lfdp`, there's an extension op which should be checked
                // and in later revs, means different opcodes.
                let xo = word & 3;

                if inst.opcode == Opcode::LDU {
                    if ra == rt || ra == 0 {
                        // TODO: xenia decodes this. what does hardware do?
                        // TODO: rpcs3 does too!
                        if !self.version.supports(IsaConstraint::CellOrXenon) {
                            return Err(DecodeError::InvalidOperand);
                        }
                    }
                }

                if inst.opcode == Opcode::STFQ || inst.opcode == Opcode::STFQU {
                    if xo == 0b00 {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                    } else {
                        // we shouldn't ever be here if the isa isn't POWER2. for All we'd have
                        // gotten to stfdp instead anyway.
                        #[cfg(test)]
                        assert_eq!(self.version, IsaVersion::RIOS2);
                        return Err(DecodeError::IncompleteDecoder);
                    }
                } else if inst.opcode == Opcode::LFDP {
                    if xo == 0b00 {
                        if rt & 1 != 0 {
                            return Err(DecodeError::InvalidOperand);
                        }
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                    } else if xo == 0b10 || xo == 0b11 {
                        // VSX loads (lxsd etc)
                        return Err(DecodeError::IncompleteDecoder);
                    } else {
                        // xo == 1
                        return Err(DecodeError::InvalidOpcode);
                    }
                } else if inst.opcode == Opcode::LFQU {
                    if xo == 0b00 {
                        if !(self.version == IsaVersion::All || self.version == IsaVersion::RIOS2) {
                            return Err(DecodeError::InvalidOperand);
                        }
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                    } else {
                        // we're in opcode 57, which (afaik) only has one op defined. so bail.
                        return Err(DecodeError::InvalidOpcode);
                    }
                } else {
                    inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                }
                // `ea` is computed from `ra` + `exts(ds || 0b00)`
                inst.operands[1] = Some(Operand::MemoryDisp { base: Register { reg: ra as u8 }, disp: (ds << 2) as i16 });
            }
            Format::X => {
                let rt = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let rb = (word >> 11) & 0x1f;
                let _xo = (word >> 1) & 0x1_ff;
                let lk = word & 1;

                // extension instructions interpret bits out of X-form in interesting ways.
                // sometimes.
                match opc {
                    /*
                     * POWER1, POWER2
                     */
                    Opcode::RLMI => {
                        // rlmi only existed in the POWER family architecture (that is, POWER +
                        // POWER2). so says AIX 5.3 aka alangref.pdf.
                        if !self.version.supports(IsaConstraint::POWER) {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        let mb = (word >> 6) & 0x1f;
                        let me = (word >> 1) & 0x1f;
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                        inst.operands[3] = Some(Operand::Imm8(mb as u8));
                        inst.operands[4] = Some(Operand::Imm8(me as u8));
                        inst.rc = lk != 0;
                    }
                    Opcode::SRQ |
                    Opcode::SLEQ |
                    Opcode::SREQ |
                    Opcode::SLLQ |
                    Opcode::SRLQ |
                    Opcode::SLE |
                    Opcode::SRE |
                    Opcode::SLQ |
                    Opcode::SRAQ |
                    Opcode::SREA |
                    Opcode::MASKG |
                    Opcode::MASKIR |
                    Opcode::RRIB => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::SLLIQ |
                    Opcode::SRAIQ |
                    Opcode::SRLIQ |
                    Opcode::SLIQ |
                    Opcode::SRIQ => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::Imm8(rb as u8));
                        inst.rc = lk != 0;
                    }
                    Opcode::CLI |
                    Opcode::CLF => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    Opcode::DCLST => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    Opcode::CLCS => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                    }
                    Opcode::DIV |
                    Opcode::DIVS |
                    Opcode::DOZ => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::LSCBX |
                    Opcode::RAC => {
                        inst.rc = lk != 0;
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::LBDX |
                    Opcode::LHDX |
                    Opcode::LWDX => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::LDDX => {
                        if self.version != IsaVersion::e500mc && self.version != IsaVersion::All {
                            return Err(DecodeError::InvalidOpcode);
                         }

                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::MUL => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));

                        inst.opcode = Opcode::MUL;
                        let oe = (word >> 10) & 1;
                        inst.oe = oe != 0;
                        inst.rc = lk != 0;
                    }
                    /* end of POWER/POWER2 instructions */
                    /* a few SLB-related (Power AS?) instructions */
                    Opcode::SLBIE => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    Opcode::SLBIA => {
                        /* no operands */
                    }
                    Opcode::SLBMFEE |
                    Opcode::SLBMFEV |
                    Opcode::SLBMTE => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    /* and the end of those */
                    Opcode::SYNC => {
                        if self.version.supports(IsaConstraint::PowerIsa203) {
                            inst.operands[0] = Some(Operand::LL(SyncControl::from_bits(rt as u8 & 0b11)));
                        }
                    }
                    /*
                     * CMP // BF, L, RA, RB
                     * CMPL // BF, L, RA, RB
                     */
                    Opcode::CMP |
                    Opcode::CMPL => {
                        let bf = rt >> 2;
                        let l = rt & 1;
                        if l == 1 && !self.version.supports(IsaConstraint::Ppc64) {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.operands[0] = Some(Operand::CrField(bf as u8));
                        inst.operands[1] = Some(Operand::Imm8(l as u8));
                        inst.operands[2] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[3] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    /*
                     * // operands: RA, RS, RB
                     * AND
                     * XOR
                     * NAND
                     * OR // v2.03 mentions PPR_PRI as a new feature when `or Rx, Rx, Rx`, w/ Rx=1, Rx=6, Rx=2
                     * NOR
                     * EQV
                     * ANDC
                     * ORC
                     *
                     * [Category: 64-Bit]
                     * // operands: RA, RS, RB
                     * SLD
                     * SRD
                     * SRAD
                     */
                    Opcode::AND |
                    Opcode::ANDC |
                    Opcode::NAND |
                    Opcode::XOR |
                    Opcode::EQV |
                    Opcode::OR |
                    Opcode::ORC |
                    Opcode::NOR |
                    Opcode::SLD |
                    Opcode::SRD |
                    Opcode::SRAD => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }

                    /* ISA v2.03
                     * // operands: RA, RS
                     * EXTSB
                     * EXTSH
                     * CNTLZW
                     *
                     * EXTSW // RA, RS [64-Bit]
                     * CNTLZD // RA, RS [Base.Phased-In]
                     * POPCNTB // RA, RS [Base.Phased-In]
                     * SLW
                     * SRW
                     * SRAWI // RA, RS, SH
                     * SRAW // RA, RS, RB
                     */
                    Opcode::CNTLZW |
                    Opcode::CNTLZD |
                    Opcode::EXTSB |
                    Opcode::EXTSH |
                    Opcode::EXTSW => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.rc = lk != 0;
                    }
// TODO:
//                    Opcode::SRL |
                    Opcode::SLW |
                    Opcode::SRW |
                    Opcode::SRAW => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::SRAWI => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::Imm8(rb as u8));
                        inst.rc = lk != 0;
                    }
                    /*
                     * at least v2.01, also in older Power by a different mnemonic.
                     * // RS, RA, NB
                     * LSWI
                     * STSWI
                     *
                     * TW // TO, RA, RB
                     * TD // TO, RA, RB
                     */
                    Opcode::LSWI | Opcode::STSWI => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::RegisterOrZero(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::Imm8(if rb == 0 { 32 } else { rb as u8 }));
                    }
                    // v2.03 3.2.2.1 Obsolete Data Cache Instructions [Category: Vector.Phased-Out]
                    /*
                     * 4. [Category: Floating-Point]
                     * // BF
                     * mcrxr
                     * // RT, RA
                     * mfapidi
                     * mtdcrux
                     * mfdcrux
                     * // FRS, RA, RB
                     * lfsx
                     * lfsux
                     * lfdx
                     * lfdux
                     * stfsx
                     * stfsux
                     * stfdx
                     * stfdux
                     * stfiwx
                     * // FRT, FRB
                     * fmr
                     * fneg
                     * fabs
                     * fnabs
                     * frsp
                     * fctid
                     * fctidz
                     * fctiw
                     * fctliwz
                     * // FRT, FRB [Floating-Point.Phased-In
                     * fcfid
                     * frin
                     * frip
                     * friz
                     * frim
                     * // operands: BF, FRA, FRB
                     * fcmpu
                     * fcmpo
                     *
                     * .. skipping 5.9.3 Vector Logical Instructions .. see below
                     * .. skipping 6.3.9 SPE Instruction Set .. see below
                     * .. skipping "Vector .. " for expedience .. Chapter 7 v2.03 page 259 (PDF: 282)
                     */
                    Opcode::MTFSB0 | Opcode::MTFSB1 => {
                        inst.operands[0] = Some(Operand::Imm8(rt as u8));
                        inst.rc = lk != 0;
                    }
                    Opcode::MCRXR => {
                        inst.operands[0] = Some(Operand::CrField(rt as u8 >> 2));
                    }
                    Opcode::MTFSFI => {
                        inst.operands[0] = Some(Operand::FpscrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::Imm8((rb >> 1) as u8));
                        inst.rc = lk != 0;
                    }
                    Opcode::FCMPO | Opcode::FCMPU => {
                        inst.operands[0] = Some(Operand::CrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                    }
                    Opcode::FCTID | Opcode::FCTIDZ |
                    Opcode::FCTIDU | Opcode::FCTIDUZ |
                    Opcode::FCFID => {
                        if !self.version.supports(IsaConstraint::Ppc64) {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::FRSP | Opcode::FCTIW | Opcode::FCTIWU | Opcode::FCTIWZ | Opcode::FCTIWUZ |
                    Opcode::DCFFIX | Opcode::DCTFIX |
                    Opcode::FMR | Opcode::FNEG | Opcode::FABS | Opcode::FNABS => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::LFSX | Opcode::LFDX | Opcode::LFSUX | Opcode::LFDUX |
                    Opcode::STFSX | Opcode::STFDX | Opcode::STFSUX | Opcode::STFDUX |
                    Opcode::STFIWX | Opcode::STFQUX => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::FCPSGN |
                    Opcode::DADD | Opcode::DSUB | Opcode::DMUL | Opcode::DDIV => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::FCFIDU | Opcode::FCFIDS | Opcode::FCFIDUS |
                    Opcode::FRIM | Opcode::FRIN |
                    Opcode::FRIP | Opcode::FRIZ |
                    Opcode::DCTDP | Opcode::DRSP |
                    Opcode::DXEX => {
                        if !self.version.supports(IsaConstraint::Fpu) {
                            // some floating point opcodes (frim, frin, frip, friz) are only v2.03
                            // and later, but also require an FPU to be present. e500 and friends
                            // do not meet this bar, but the most convenient place to check that is
                            // here.
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::DCFFIXQ |
                    Opcode::DCTQPQ => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 & !1 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::DCTFIXQ => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::DRDPQ => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 & !1 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::DXEXQ => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::DIEX => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::DIEXQ => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 & !1 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::DADDQ | Opcode::DSUBQ | Opcode::DMULQ | Opcode::DDIVQ => {
                        if rt & 1 != 0 || ra & 1 != 0 || rb & 1 != 0 {
                            return Err(DecodeError::InvalidOpcode);
                        }

                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::DCMPO | Opcode::DCMPU => {
                        inst.operands[0] = Some(Operand::CrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                    }
                    Opcode::DCMPOQ | Opcode::DCMPUQ => {
                        inst.operands[0] = Some(Operand::CrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 & !1 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                    }
                    Opcode::DTSTEX => {
                        inst.operands[0] = Some(Operand::CrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                    }
                    Opcode::FTDIV |
                    Opcode::DTSTSF => {
                        inst.operands[0] = Some(Operand::CrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                    }
                    Opcode::DTSTSFQ => {
                        inst.operands[0] = Some(Operand::CrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                    }
                    Opcode::DTSTEXQ => {
                        inst.operands[0] = Some(Operand::CrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 & !1 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                    }
                    Opcode::FTSQRT => {
                        inst.operands[0] = Some(Operand::CrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                    }
                    /* TODO: not sure when exactly this was added (ppc?)
                     */
                    Opcode::MCRFS => {
                        inst.operands[0] = Some(Operand::CrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::FpscrField((ra >> 2) as u8));
                    }
                    /* Vector (AltiVec, also Power v2.03)
                     * lvsl
                     * ... many more
                     */
                    Opcode::LVX |
                    Opcode::LVEBX | Opcode::LVEHX | Opcode::LVEWX |
                    Opcode::STVX |
                    Opcode::LVXL | Opcode::STVXL |
                    Opcode::STVEBX | Opcode::STVEHX | Opcode::STVEWX |
                    Opcode::LVSL | Opcode::LVSR |
                    Opcode::LVLX |// Opcode::LVLXL |
                    Opcode::LVRX |// Opcode::LVRXL |
                    Opcode::STVRX | Opcode::STVRXL |
                    Opcode::STVLX | Opcode::STVLXL => {
                        inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::STVEPXL => {
                        // with some dismay, ALTIVECPOWERISAPEM.pdf lists opc=0x3f, xo=0x307 is
                        // STVEPXL, but Xenia and RPCS3 say it's "lvlxl", which no manual defines.
                        if self.version == IsaVersion::Xenon || self.version == IsaVersion::Cell {
                            inst.opcode = Opcode::LVLXL;
                        } else if !self.version.supports(IsaConstraint::AltiVec) {
                            return Err(DecodeError::InvalidOpcode);
                        }

                        inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::STVEPX => {
                        // with some dismay, ALTIVECPOWERISAPEM.pdf lists opc=0x3f, xo=0x327 is
                        // STVEPX, but Xenia and RPCS3 say it's "lvrxl", which no manual defines.
                        if self.version == IsaVersion::Xenon || self.version == IsaVersion::Cell {
                            inst.opcode = Opcode::LVRXL;
                        } else if !self.version.supports(IsaConstraint::AltiVec) {
                            return Err(DecodeError::InvalidOpcode);
                        }

                        inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    /* Embedded Floating-Point (EVX-Form)
                     *
                     * [SPE.Embedded Float Scalar Single]
                     * // operands: RT, RA
                     * EFSABS
                     * EFSNEG
                     * EFSNABS
                     * // operands RT, RA, RB
                     * EFSADD
                     * EFSSUB
                     * EFSMUL
                     * EFSDIV
                     * // operands BF, RA, RB
                     * EFSCMPGT
                     * EFSCMPLT
                     * EFSCMPEQ
                     * EFSTSTGT
                     * EFSTSTLT
                     * EFSTSTEQ
                     * // operands RT, RB
                     * EFSCFSI
                     * EFSCFUI
                     * EFSCFSF
                     * EFSCFUF
                     * EFSCTSI
                     * EFSCTUI
                     * EFSCTSIZ
                     * EFSCTUIZ
                     * EFSCTSF
                     * EFSCTUF
                     * // [SPE.Embedded Float Scalar Double]
                     * // operands RT, RA
                     * EFDABS
                     * EFDNEG
                     * EFDNABS
                     * // operands: RT, RA, RB
                     * EFDADD
                     * EFDSUB
                     * EFDMUL
                     * EFDDIV
                     * // operands: BF, RA, RB
                     * EFDCMPGT
                     * EFDCMPLT
                     * EFDCMPEQ
                     * EFDTSTGT
                     * EFDTSTLT
                     * EFDTSTEQ
                     *
                     * // operands: RT, RB
                     * EFDCFSI
                     * EFDCFUI
                     * EFDCFSID
                     * EFDCFUID
                     * EFDCFSF
                     * EFDCFUF
                     * EFDCTSI
                     * EFDCTUI
                     * EFDCTSIDZ
                     * EFDCTUIDZ
                     * EFDCTSIZ
                     * EFDCTUIZ
                     * EFDCSF
                     * EFDCTUF
                     * EFDCFS
                     * EFSCFD
                     *
                     */
                    /* Fixed-Point Instructions
                     *
                     * // Determine Leftmost Zero Byte
                     * DLMZB
                     *
                     * // Legacy Integer Multiply-Accumulate Instructions
                     * MULCHW
                     * MULCHWU
                     * MULHHW
                     * MULHHWU
                     * MULLHW
                     * MULLHWU
                     *
                     * // unure what exactly
                     * ICBI
                     * ICBT [Embedded]
                     * DCBT [Server, Embedded] (AND DIFFERENT OPERANDS FOR EACH?!)
                     * DCBTST [Server, Embedded] (AND DIFFERENT OPERANDS FOR EACH?!)
                     * DCBZ
                     * DCBST
                     */
                    Opcode::DSS => {
                        inst.operands[0] = Some(Operand::Imm8(rt as u8 & 0b11));
                        if rt >> 4 == 1 {
                            inst.opcode = Opcode::DSSALL;
                        }
                    }
                    Opcode::DST => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rb as u8 }));
                        inst.operands[2] = Some(Operand::Imm8(rt as u8 & 0b11));
                        if rt >> 4 == 1 {
                            inst.opcode = Opcode::DSTT;
                        }
                    }
                    Opcode::DSTST => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rb as u8 }));
                        inst.operands[2] = Some(Operand::Imm8(rt as u8 & 0b11));
                        if rt >> 4 == 1 {
                            inst.opcode = Opcode::DSTSTT;
                        }
                    }
                    Opcode::ICBI |
                    Opcode::DCBI => {
                        inst.operands[0] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::DCBF => {
                        inst.operands[0] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                        if self.version.supports(IsaConstraint::PowerIsa205) {
                            // in Power v2.05 this field was extended to two bits (L=3 is now
                            // valid and means `dcbflp`)
                            inst.operands[1] = Some(Operand::Imm8(rt as u8 & 0b11));
                        } else if self.version.supports(IsaConstraint::PowerIsa202) {
                            // before Power v2.02 there was no L operand to `dcbf`. in 2.02 and
                            // later, L=1 means the alias `dcbfl`.
                            inst.operands[1] = Some(Operand::Imm8(rt as u8 & 0b1));
                        }
                    }
//                    Opcode::ICBT |
                    Opcode::DCBZ => {
                        // DCBZ "existed" as far back as PowerPC (is in
                        // SR28-5124-01_The_PowerPC_Architecture_May94.pdf), but was part of the
                        // Virtual Instruction Set until 2.03. it's decoded as long as it was in
                        // the VISA to match with other decoders, objdump, etc.
                        inst.operands[0] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });

                        // Xenia only decodes `dcbz` when rt=0, and indicates a `dcbz128` when
                        // rt=1, decoding nothing otherwise. RPCS3 seems to decode in any case?
                        if self.version == IsaVersion::Xenon && rt != 0 {
                            if rt == 1 {
                                inst.opcode = Opcode::DCBZ128;
                            } else {
                                return Err(DecodeError::InvalidOperand);
                            }
                        }
                    }
                    Opcode::DCBA |
                    Opcode::DCBST => {
                        inst.operands[0] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::DCBT => {
                        // TODO: assuming [Server] encoding
                        inst.operands[0] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                        // in Power v2.05 the TH field was extended to 5 bits.
                        let th = rt as u8 & 0b11111;
                        if self.version.supports(IsaConstraint::PowerIsa205) {
                            inst.operands[1] = Some(Operand::Imm8(th));
                        } else if self.version.supports(IsaConstraint::PowerIsa203) {
                            // ... but until 2.05, it was only 4 bits.
                            inst.operands[1] = Some(Operand::Imm8(th & !0b1_0000));
                        } else if self.version.supports(IsaConstraint::PowerIsa200) {
                            // the TH field, aka Touch Hint, was defined on `dcbt` first in v2.00
                            // for Power AS. later, and above, here, this finally became "public"
                            // in v2.03(?).
                            inst.opcode = Opcode::DCBT_AS;
                            inst.operands[1] = Some(Operand::Imm8(th & 0b11));
                        }
                    }
                    Opcode::DCBTLS => {
                        let th = rt as u8 & 0b1111;
                        inst.operands[0] = Some(Operand::Imm8(th as u8 & 0b1111));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::DCBTST => {
                        // TODO: assuming [Server] encoding
                        inst.operands[0] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                        // like `dcbt` above, `dcbtst` gets a 4-bit hint in 2.03, expanded to 5-bit
                        // in 2.05.
                        let th = rt as u8 & 0b11111;
                        if self.version.supports(IsaConstraint::PowerIsa205) {
                            inst.operands[1] = Some(Operand::Imm8(th));
                        } else if self.version.supports(IsaConstraint::PowerIsa200) {
                            inst.operands[1] = Some(Operand::Imm8(th & !0b1_0000));
                        } else if self.version.supports(IsaConstraint::POWER) {
                            // before Power v2.00 or so this hint wasn't supported at all. mostly:
                            // this is not supported if the IsaVersion is RIOS/RIOS2.
                            return Err(DecodeError::InvalidOpcode);
                        }
                    }
                    /*
                     * // External Access Instructions [External Control]
                     * ECIWX
                     * ECOWX
                     */
                    Opcode::ECIWX | Opcode::ECOWX => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    /*
                     * // unsure what extension yet
                     *
                     * E_SLWI
                     * E_RLWI
                     * E_RLW
                     *
                     * // "Storage Control" maybe?
                     * SYNC
                     * EIEIO [Server]
                     * MBAR [Embedded]
                     * WAIT [Wait]
                     *
                     */
                    Opcode::EIEIO => {
                        // TODO: the 2.03 manual describes eieio and mbar 0 as operating
                        // differently, implicitly? what is the right thing to do for that version
                        // in the case of rt=0..
                        if self.version.supports(IsaConstraint::Embedded) &&
                            !self.version.supports(IsaConstraint::PowerIsa30) &&
                            rt != 0 {

                            let mo = rt as u8;
                            // see v2.03 and `Embedded`.
                            inst.opcode = Opcode::MBAR;
                            inst.operands[0] = Some(Operand::Imm8(mo));
                        }
                    }
                    /*
                     * // Fixed-Point Processor
                     * MTMSR
                     * MTMRSD
                     * MFMSR
                     * SLBIE
                     * SLBIA
                     * SLBMTE
                     * SLBMFEV
                     * SLBMFEE
                     * MTSR
                     * MTSRIN
                     * MFSR
                     * MFSRIN
                     * TLBIE [Server]
                     * TLBIEL [Server]
                     * TLBIA
                     * TLBSYNC
                     * RFDI [Embedded.Enhanced Debug]
                     * MTDCRX
                     * MFDCRX
                     * MFMSR
                     * WRTEE
                     * WRTEEI
                     */
                    Opcode::MTSR => {
                        inst.operands[0] = Some(Operand::Imm8(ra as u8 & 0b1111));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                    }
                    Opcode::MTSRIN => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    Opcode::MFSR => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Imm8(ra as u8 & 0b1111));
                    }
                    Opcode::MFSRI => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    Opcode::MFSRIN => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    Opcode::MTSRD => {
                        // HELP: actual citations for MTSRD are scarce. it's not in the RS/6000
                        // docs, nor Power v2.02+, nor PowerPC, so this is mostly rederived from
                        // binutils..
                        if !self.version.supports(IsaConstraint::Ppc64) {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.operands[0] = Some(Operand::Imm8(ra as u8 & 0b1111));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                    }
                    Opcode::MTSRDIN => {
                        if !self.version.supports(IsaConstraint::Ppc64) {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    Opcode::TLBIE => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rb as u8 }));

                        // later Power ISA versions add parameters to tlbie. 2.01+ add an L field
                        // to indicate page size for the invalidation, and 2.06+ change the L field
                        // into a register.

                        if self.version.supports(IsaConstraint::PowerIsa206) {
                            inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                        } else if self.version.supports(IsaConstraint::PowerIsa202) {
                            inst.operands[1] = Some(Operand::Imm8(rt as u8 & 1));
                        } else if self.version.supports(IsaConstraint::POWER) {
                            inst.opcode = Opcode::TLBI;
                            inst.operands[1] = inst.operands[0];
                            inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                        } else if self.version == IsaVersion::Xenon {
                            // another case of a cache-related instruction that might be
                            // intentionally.. or unintentionally.. ignored in Xenia?
                            return Err(DecodeError::InvalidOpcode);
                        } else {
                            // not POWER1, not POWER2, so v2.0 to v2.02. so just the register and no large-page support?
                        }
                    }
                    /*
                     *
                     * LBEPX
                     * LHEPX
                     * LWEPX
                     * LDEPX
                     * STBEPX
                     * STHEPX
                     * STWEPX
                     * STDEPX
                     * DCBSTEP
                     * DCBTEP
                     * DCBFEP
                     * DCBTSTEP
                     * ICBIEP
                     * DCBZEP
                     * LFDEPX
                     * STFDEPX
                     * EVLDDEPX
                     * EVSTDDEPX
                     * LVEPX
                     * LVEPXL
                     * STVEPX
                     * STVEPXL
                     *
                     * // TODO: ?? Cache Management Instructions ???
                     * DCBI
                     * DCBTLS
                     * DCBTSTLS
                     * ICBTLS
                     * ICBLC
                     * DCBLC
                     * TLBIVAX
                     * TLBRE
                     * TLBSX
                     * TLBSYNC
                     * TLBWE
                     */
                    Opcode::TLBRE |
                    Opcode::TLBWE => {
                        // no operands on either of these
                    }
                    Opcode::TLBSX |
                    Opcode::TLBIVAX => {
                        inst.operands[0] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    /*
                     * 9.3 Processor Control Instructions
                     * MSGSND
                     * MSGCLR
                     */
                    Opcode::MSGCLR |
                    Opcode::MSGSND |
                    Opcode::MSGCLRP |
                    Opcode::MSGSNDP => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    /*
                     * A.1 Embedded Cache Initialization
                     * DCI
                     * ICI
                     *
                     * A.3 Embedded Cache Debug Instructions
                     * DCREAD
                     *
                     * smaller reg1 (bf):
                     * E_CMPHL
                     * E_CMPH
                     *
                     * two regs:
                     * TLBSX
                     * TLBIVAX
                     * ICREAD
                     */
                    Opcode::LBZX |
                    Opcode::LHZX |
                    Opcode::LHAX |
                    Opcode::LWZX |
                    Opcode::LWAX |
                    Opcode::LDX |
                    Opcode::STBX |
                    Opcode::STHX |
                    Opcode::STWX |
                    Opcode::STDX => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::LBZUX |
                    Opcode::LHZUX |
                    Opcode::LHAUX |
                    Opcode::LWZUX |
                    Opcode::LWAUX |
                    Opcode::LDUX |
                    Opcode::STBUX |
                    Opcode::STHUX |
                    Opcode::STWUX |
                    Opcode::STDUX |
                    Opcode::LHBRX |
                    Opcode::LDBRX |
                    Opcode::STHBRX |
                    Opcode::STDBRX |
                    Opcode::LSWX |
                    Opcode::STSWX |
                    // start 64-bit Load and Reserver and Store Conditional Instructions
                    Opcode::STDCX |
                    Opcode::STWCX |
                    Opcode::LDARX |
                    Opcode::LWARX |
                    // end 64-bit Load and Reserver and Store Conditional Instructions
                    Opcode::STWBRX |
                    Opcode::LWBRX => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                        if opc == Opcode::STDCX || opc == Opcode::STWCX {
                            let isa_tolerates_lk0 = self.version != IsaVersion::All &&
                                                    self.version != IsaVersion::Xenon &&
                                                    self.version != IsaVersion::Cell;
                            if lk == 0 && isa_tolerates_lk0 {
                                return Err(DecodeError::InvalidOpcode);
                            }
                            // HELP: these are defined as always having `rc` set, and in fact only
                            // being valid with Rc=1, but xenia and rpcs3 decode them either way.
                            // so i'm assuming hardware also accepts this. does it?
                            inst.rc = true;
                        } else if opc == Opcode::LWARX || opc == Opcode::LDARX {
                            if self.version.supports(IsaConstraint::PowerIsa205) {
                                inst.operands[2] = Some(Operand::Imm8(lk as u8));
                            } else if lk != 0 && self.version != IsaVersion::Gekko {
                                return Err(DecodeError::InvalidOperand);
                            }
                        }
                    }
                    Opcode::MFMSR => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                    }
                    Opcode::MTMSR |
                    Opcode::MTMSRD => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        if self.version == IsaVersion::Xenon {
                            // the fact that there's a different `MTMSRD_Xenon` is unfortunate, but
                            // see the comment around aliasing in alias.rs .. we don't need to do
                            // this for MTMSR because there is no Xenon-specific aliasing (or
                            // alternate mnemonic!) rules.
                            if inst.opcode == Opcode::MTMSRD {
                                inst.opcode = Opcode::MTMSRD_Xenon;
                            }
                            inst.operands[1] = Some(Operand::Imm8(ra as u8 & 1));
                        } else if self.version.supports(IsaConstraint::PowerIsa200) {
                            // mtmsr and mtmsrd got a second operand in the form of `L` somewhere
                            // between PowerPC AS (note "v2.00" in the reference) and PowerPC
                            // v2.01. notably, v2.01 does not indicate `L` is *new* in 2.01,
                            // implying it came earlier, but the only earlier reference i can find
                            // is the AS/v2.00 one, which does not indicate `L` being decoded. so
                            // "added in 2.00 after Amazon" is a bit of a best guess from available
                            // docs.
                            inst.operands[1] = Some(Operand::Imm8(ra as u8 & 1));
                        }
                    }
                    Opcode::MFFS => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::TD |
                    Opcode::TW => {
                        inst.operands[0] = Some(Operand::Imm8(rt as u8));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    Opcode::STFDPX => {
                        if self.version == IsaVersion::RIOS2 {
                            inst.opcode = Opcode::STFQX;
                        } else if self.version.supports(IsaConstraint::PowerIsa205) {
                            if rt & 1 != 0 {
                                // > If FRTp is odd, the instruction form is invalid
                                //
                                // .. objdump falls back to STFQX, but only do that if we're
                                // `IsaVersion::All`:
                                if self.version == IsaVersion::All {
                                    inst.opcode = Opcode::STFQX;
                                } else {
                                    return Err(DecodeError::InvalidOperand);
                                }
                            }
                        } else {
                            // this really means POWER1
                            return Err(DecodeError::InvalidOpcode);
                        }

                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::STFDP => {
                        let xo = word & 0b11;
                        if xo != 00 {
                            return Err(DecodeError::InvalidOpcode);
                        }

                        let rt = (word >> 21) & 0x1f;
                        let ra = (word >> 16) & 0x1f;
                        let ds = (word >> 2) & 0x3fff;

                        if rt & 1 != 0 {
                            return Err(DecodeError::InvalidOperand);
                        }

                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryDisp { base: Register { reg: ra as u8 }, disp: (ds << 2) as i16 });
                    }
                    Opcode::LFQUX => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::LFDPX => {
                        if self.version == IsaVersion::RIOS2 {
                            inst.opcode = Opcode::LFQX;
                        } else if self.version.supports(IsaConstraint::PowerIsa205) {
                            if rt & 1 != 0 {
                                // > If FRTp is odd, the instruction form is invalid
                                //
                                // .. objdump falls back to LFQX, but only do that if we're
                                // `IsaVersion::All`:
                                if self.version == IsaVersion::All {
                                    inst.opcode = Opcode::LFQX;
                                } else {
                                    return Err(DecodeError::InvalidOperand);
                                }
                            }
                        } else {
                            // this really means POWER1
                            return Err(DecodeError::InvalidOpcode);
                        }

                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::MemoryIndexed {
                            base: Register { reg: ra as u8 },
                            index: Register { reg: rb as u8 },
                        });
                    }
                    Opcode::DDEDPD => {
                        inst.operands[0] = Some(Operand::Imm8((ra >> 3) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::DENBCD => {
                        inst.operands[0] = Some(Operand::Imm8((ra >> 4) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::DDEDPDQ => {
                        inst.operands[0] = Some(Operand::Imm8((ra >> 3) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rt as u8 & !1 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::DENBCDQ => {
                        inst.operands[0] = Some(Operand::Imm8((ra >> 4) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rt as u8 & !1 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                        inst.rc = lk != 0;
                    }
                    Opcode::TRECHKPT => {
                        if lk == 0 {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.rc = true;
                    }
                    Opcode::TABORT |
                    Opcode::TRECLAIM => {
                        if lk == 0 {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.rc = true;
                        inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                    }
                    Opcode::TABORTDC |
                    Opcode::TABORTWC => {
                        if lk == 0 {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.rc = true;
                        inst.operands[0] = Some(Operand::Imm8(rt as u8));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                    }
                    Opcode::TABORTDCI |
                    Opcode::TABORTWCI => {
                        if lk == 0 {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.rc = true;
                        inst.operands[0] = Some(Operand::Imm8(rt as u8));
                        inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                        let extended = (((rb as i8) << 3) >> 3) as i16;
                        inst.operands[2] = Some(Operand::ImmExts16(extended));
                    }
                    Opcode::TBEGIN => {
                        if lk == 0 {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.rc = true;
                        let a = rt as u8 & 1;
                        inst.operands[0] = Some(Operand::Imm8(a));
                    }
                    Opcode::TEND => {
                        if lk == 0 {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.rc = true;
                        let a = rt as u8 >> 4;
                        inst.operands[0] = Some(Operand::Imm8(a));
                    }
                    Opcode::TSR => {
                        if lk == 0 {
                            return Err(DecodeError::InvalidOpcode);
                        }
                        inst.rc = true;
                        let l = rt as u8 & 1;
                        inst.operands[0] = Some(Operand::Imm8(l));
                    }
                    Opcode::TCHECK => {
                        let bf = rt as u8 >> 2;
                        inst.operands[0] = Some(Operand::CrField(bf));
                    }
                    _ => {
                        // TODO: the rest?
                    }
                }
            }
            Format::XS => {
                let rs = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let sh_lo = (word >> 11) & 0x1f;
                let rc = word & 1;
                let sh_hi = (word >> 1) & 1;
                let sh = (sh_hi << 5) | sh_lo;

                inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                inst.operands[1] = Some(Operand::Register(Register { reg: rs as u8 }));
                inst.operands[2] = Some(Operand::Imm8(sh as u8));
                inst.rc = rc != 0;
            }
            Format::XO => {
                let rt = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let rb = (word >> 11) & 0x1f;
                let _xo = (word >> 1) & 0x1_ff;
                let oe = (word >> 10) & 1;
                let rc = word & 1;

                // for all XO-form other than `mulhw`, `mulhwu`, `mulhd`, `mulhdu`
                if ![Opcode::MULHW, Opcode::MULHWU, Opcode::MULHD, Opcode::MULHDU].contains(&opc) {
                    inst.oe = oe != 0;
                }

                inst.rc = rc != 0;

                inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                inst.operands[1] = Some(Operand::Register(Register { reg: ra as u8 }));
                // `neg`, `addze`, `addfze`, `subfme`, `addme` are only `rt, ra`
                // also `abs` and `nabs`, for the older deleted isntructions.
                if ![
                    Opcode::NEG, Opcode::ABS, Opcode::NABS,
                    Opcode::ADDME, Opcode::SUBFME, Opcode::ADDZE, Opcode::SUBFZE].contains(&opc) {
                    inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                }
            }
            Format::XL => {
                let bt = (word >> 21) & 0x1f;
                let ba = (word >> 16) & 0x1f;
                let bb = (word >> 11) & 0x1f;
                let _xo = (word >> 1) & 0x1_ff;
                let lk = word & 1;

                match opc {
                    Opcode::BCLR | Opcode::BCCTR => {
                        if self.version == IsaVersion::RIOS || self.version == IsaVersion::RIOS2 {
                            // in ye olde POWER/POWER2, there was just no branch hinting.
                            inst.hint_style = None;
                        } else if !self.version.supports(IsaConstraint::PowerIsa200) || self.version == IsaVersion::e500 {
                            // if the ISA is old, the BO field (namely, branch hint) interpretation
                            // is different, and yax describes that using a different set of branch
                            // opcodes.
                            inst.hint_style = Some(HintStyle::Legacy);
                        } else {
                            inst.hint_style = Some(HintStyle::PowerIsa);
                        }
                        inst.operands[0] = Some(Operand::Imm8(bt as u8));
                        inst.operands[1] = Some(Operand::CrBit(ba as u8));
                        // HELP: Power v2.02 does not indicate that the BH field for prediction
                        // hints is new, but the field was unused as of PowerPC 1994. lacking a
                        // more specific version to say this was new in, the hint is only decoded
                        // for 2.02+.
                        if self.version.supports(IsaConstraint::PowerIsa202) {
                            inst.operands[2] = Some(Operand::Imm8((bb & 0x3) as u8));
                        }
                        inst.lk = lk != 0;
                    }
                    Opcode::CRAND |
                    Opcode::CRANDC |
                    Opcode::CRNAND |
                    Opcode::CRXOR |
                    Opcode::CRNOR |
                    Opcode::CREQV |
                    Opcode::CROR |
                    Opcode::CRORC => {
                        inst.operands[0] = Some(Operand::CrBit(bt as u8));
                        inst.operands[1] = Some(Operand::CrBit(ba as u8));
                        inst.operands[2] = Some(Operand::CrBit(bb as u8));
                    }
                    Opcode::MCRF => {
                        inst.operands[0] = Some(Operand::CrField((bt >> 2) as u8));
                        inst.operands[1] = Some(Operand::CrField((ba >> 2) as u8));
                    }
                    // HELP: is there any implementation with hrfid that is not 64-bit..?
                    Opcode::HRFID |
                    Opcode::RFID => {
                        if !self.version.supports(IsaConstraint::Ppc64) {
                            return Err(DecodeError::InvalidOpcode);
                        }
                    }
                    _ => {
                        // TODO: the rest?
                    }
                }
            }
            Format::XFL => {
                let l = (word >> 25) & 1;
                let flm = (word >> 17) & 0xff;
                let w = (word >> 16) & 1;
                let rb = (word >> 11) & 0x1f;
                let _xo = (word >> 1) & 0x1_ff;
                let rc = word & 1;

                inst.operands[0] = Some(Operand::Imm8(flm as u8));
                inst.operands[1] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                // additional fields were added to `mtfsf` in 2.05.
                if self.version.supports(IsaConstraint::PowerIsa205) {
                    inst.operands[2] = Some(Operand::Imm8(l as u8));
                    inst.operands[3] = Some(Operand::Imm8(w as u8));
                }
                inst.rc = rc != 0;
            }
            Format::XFX => {
                let rt = (word >> 21) & 0x1f;
                let imm_b11 = (word >> 11) & 0x3_ff;
                let _xo = (word >> 1) & 0x1_ff;
                let _lk = word & 1;

                match opc {
                    Opcode::MTSPR => {
                        let imm_lo = imm_b11 & 0x1f;
                        let imm_hi = (imm_b11 >> 5) & 0x1f;
                        let spr_nr = (imm_lo << 5) | imm_hi;
                        inst.operands[0] = Some(Operand::SPR(SPR { reg: spr_nr as u16 }));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                    }
                    Opcode::MFSPR => {
                        let imm_lo = imm_b11 & 0x1f;
                        let imm_hi = (imm_b11 >> 5) & 0x1f;
                        let spr_nr = (imm_lo << 5) | imm_hi;
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::SPR(SPR { reg: spr_nr as u16 }));
                    }
                    // TODO: if xfx field 0 is ff
                    Opcode::MTCRF => {
                        let fxm = (imm_b11 >> 1) & 0xff;
                        // HELP: it seems like gekko might interpret b11 as a dont-care rather than
                        // picking mtocrf
                        let supports_mtocrf = self.version.supports(IsaConstraint::Ppc) && self.version != IsaVersion::Gekko;
                        if imm_b11 & 0b10_0000_0000 != 0 && supports_mtocrf {
                            // see doc comment on IsaVersion
                            inst.opcode = Opcode::MTOCRF;

                            let rest = ((imm_b11 & 0x1_ff) >> 1) as u8;
                            if rest.count_ones() != 1 {
                                return Err(DecodeError::InvalidOpcode);
                            }

                            // in what is perhaps the most confusing assembly convention i've seen,
                            // the CR field mask is printed as an immediate, rather than the one
                            // CRF that the field selects. even though this field is a one-hot mask
                            // under `mtocrf`, it is not displayed as or parsed as a `crN` field
                            // like a normal condition register field. so, while it would be most
                            // accurate to report this as `Operand::CrField`, it would need a
                            // one-off (well, two-off)
                        }
                        inst.operands[0] = Some(Operand::CrMask(fxm as u8));
                        inst.operands[1] = Some(Operand::Register(Register { reg: rt as u8 }));
                    }
                    Opcode::MFCR => {
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));

                        // v2.01 Book I Appendix F:
                        // > The following instructions in the PowerPC User Instruction Set
                        // > Architecture are new; they are not in the POWER Architecture.
                        let supports_mfocrf = self.version.supports(IsaConstraint::Ppc) && self.version != IsaVersion::Gekko;
                        if imm_b11 & 0b10_0000_0000 != 0 && supports_mfocrf {
                            if self.version.includes_ppc() {
                                inst.opcode = Opcode::MFOCRF;
                                let rest = ((imm_b11 & 0x1_ff) >> 1) as u8;
                                if rest.count_ones() != 1 {
                                    return Err(DecodeError::InvalidOpcode);
                                }
                                // see the note on MTOCRF above about why this is a `CrMask`
                                // instead of `CrField`...
                                inst.operands[1] = Some(Operand::CrMask(rest as u8));
                            } else {
                                return Err(DecodeError::InvalidOpcode);
                            }
                        }
                    }
                    Opcode::MFTB => {
                        // TODO: Server.Phased-out
                        // book v2.03:
                        // > Processors for which mfspr cannot be used to read the Time Base
                        // > include the following.
                        // > - 601
                        // > - POWER3
                        // >
                        // .. the book goes on to remark that the 601 is expected to use !MFTB
                        // anyway, because the illegal instruction handler is expected to emulate
                        // both `mftb` and the `Time Base` in the first place. "new programs should
                        // use mfspr instead of mftb".
                        inst.operands[0] = Some(Operand::Register(Register { reg: rt as u8 }));
                        // time base is also accessible as an SPR, but it is a ten-bit field so
                        // reproduce it faithfully. unfortunately, also, the low and high five bits
                        // are swapped..?
                        let tbr = (word >> 11) & 0x3ff;
                        let tbr_hi = tbr & 0x1f;
                        let tbr_lo = (tbr >> 5) & 0x1f;
                        let tbr = (tbr_hi << 5) | tbr_lo;
                        inst.operands[1] = Some(Operand::ImmU16(tbr as u16));
                    }
                    // TODO: MTDCR, MFDCR
                    _ => {
                        unreachable!("other xfx-form opcodes");
                    }
                }
            }
            Format::M => {
                let rs = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let sh = (word >> 11) & 0x1f;
                let mb = (word >> 6) & 0x1f;
                let me = (word >> 1) & 0x1f;
                let rc = word & 1;

                inst.rc = rc != 0;

                inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                inst.operands[1] = Some(Operand::Register(Register { reg: rs as u8 }));
                if inst.opcode == Opcode::RLWNM {
                    inst.operands[2] = Some(Operand::Register(Register { reg: sh as u8 }));
                } else {
                    inst.operands[2] = Some(Operand::Imm8(sh as u8));
                }
                inst.operands[3] = Some(Operand::Imm8(mb as u8));
                inst.operands[4] = Some(Operand::Imm8(me as u8));
            }
            Format::E => {
                let rs = (word >> 21) & 0x1f;
                let _ra = (word >> 16) & 0x1f;
                let rt = (word >> 11) & 0x1f;

                inst.operands[0] = None;
                inst.operands[1] = None;
                inst.operands[2] = None;
                inst.operands[3] = None;

                match inst.opcode {
                    Opcode::WRTEE => {
                        inst.operands[0] = Some(Operand::Register(Register {reg: rs as u8 }));
                    }
                    Opcode::WRTEEI => {
                        inst.operands[0] = Some(Operand::Imm8((rt >> 4) as u8));
                    }
                    _ => {
                    }
                }
            }
            Format::MD => {
                let rs = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let sh_lo = (word >> 11) & 0x1f;
                let sh_hi = (word >> 1) & 0x1;

                let mb_lo = (word >> 6) & 0x1f;
                let mb_hi = (word >> 5) & 0x1;
                let mb = (mb_hi << 5) | mb_lo;
                let rc = word & 1;

                inst.rc = rc != 0;
                let sh = (sh_hi << 5) | sh_lo;

                inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                inst.operands[1] = Some(Operand::Register(Register { reg: rs as u8 }));
                inst.operands[2] = Some(Operand::Imm8(sh as u8));
                inst.operands[3] = Some(Operand::Imm8(mb as u8));
            }
            Format::MDS => {
                let rs = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let rb = (word >> 11) & 0x1f;
                let mb_lo = (word >> 6) & 0x1f;
                let mb_hi = (word >> 5) & 0x1;
                let mb = (mb_hi << 5) | mb_lo;
                let rc = word & 1;

                inst.rc = rc != 0;

                inst.operands[0] = Some(Operand::Register(Register { reg: ra as u8 }));
                inst.operands[1] = Some(Operand::Register(Register { reg: rs as u8 }));
                inst.operands[2] = Some(Operand::Register(Register { reg: rb as u8 }));
                inst.operands[3] = Some(Operand::Imm8(mb as u8));
            }
            Format::VX => {
                let rt = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let rb = (word >> 11) & 0x1f;

                match inst.opcode {
                    Opcode::VSL | Opcode::VSLO |
                    Opcode::VSR | Opcode::VSRO |

                    Opcode::VADDCUW |
                    Opcode::VADDSBS | Opcode::VADDSHS | Opcode::VADDSWS |
                    Opcode::VADDUBM | Opcode::VADDUHM | Opcode::VADDUWM |
                    Opcode::VADDUBS | Opcode::VADDUHS | Opcode::VADDUWS |
                    Opcode::VSUBCUW |
                    Opcode::VSUBSBS | Opcode::VSUBSHS | Opcode::VSUBSWS |
                    Opcode::VSUBUBM | Opcode::VSUBUHM | Opcode::VSUBUWM |
                    Opcode::VSUBUBS | Opcode::VSUBUHS | Opcode::VSUBUWS |

                    Opcode::VMULESB | Opcode::VMULESH |
                    Opcode::VMULEUB | Opcode::VMULEUH |
                    Opcode::VMULOSB | Opcode::VMULOSH |
                    Opcode::VMULOUB | Opcode::VMULOUH |

                    Opcode::VSUMSWS | Opcode::VSUM2SWS |
                    Opcode::VSUM4SBS | Opcode::VSUM4SHS | Opcode::VSUM4UBS |

                    Opcode::VAVGSB | Opcode::VAVGSH | Opcode::VAVGSW |
                    Opcode::VAVGUB | Opcode::VAVGUH | Opcode::VAVGUW |
                    Opcode::VMAXSB | Opcode::VMAXSH | Opcode::VMAXSW |
                    Opcode::VMAXUB | Opcode::VMAXUH | Opcode::VMAXUW |
                    Opcode::VMINSB | Opcode::VMINSH | Opcode::VMINSW |
                    Opcode::VMINUB | Opcode::VMINUH | Opcode::VMINUW |

                    Opcode::VAND | Opcode::VANDC |
                    Opcode::VNOR | Opcode::VOR | Opcode::VXOR |
                    Opcode::VRLB | Opcode::VRLH | Opcode::VRLW |
                    Opcode::VSLB | Opcode::VSLH | Opcode::VSLW |
                    Opcode::VSRAB | Opcode::VSRAH | Opcode::VSRAW |
                    Opcode::VSRB | Opcode::VSRH | Opcode::VSRW |

                    Opcode::VADDFP | Opcode::VSUBFP |
                    Opcode::VMAXFP | Opcode::VMINFP |

                    Opcode::VPKSHSS | Opcode::VPKSHUS |
                    Opcode::VPKSWSS | Opcode::VPKSWUS |
                    Opcode::VPKUHUM | Opcode::VPKUHUS |
                    Opcode::VPKUWUM | Opcode::VPKUWUS |
                    Opcode::VMRGHB | Opcode::VMRGHH | Opcode::VMRGHW |
                    Opcode::VMRGLB | Opcode::VMRGLH | Opcode::VMRGLW |
                    Opcode::VPKPX => {
                        inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::VR(VR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::VR(VR { reg: rb as u8 }));
                    }
                    Opcode::VRFIM | Opcode::VRFIN | Opcode::VRFIP | Opcode::VRFIZ |
                    Opcode::VEXPTEFP | Opcode::VLOGEFP |
                    Opcode::VREFP | Opcode::VRSQRTEFP |
                    Opcode::VUPKLPX | Opcode::VUPKLSB |
                    Opcode::VUPKLSH |
                    Opcode::VUPKHPX | Opcode::VUPKHSB |
                    Opcode::VUPKHSH => {
                        inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::VR(VR { reg: rb as u8 }));
                    }
                    Opcode::VCTSXS | Opcode::VCTUXS |
                    Opcode::VCFSX | Opcode::VCFUX => {
                        inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::VR(VR { reg: rb as u8 }));
                        inst.operands[2] = Some(Operand::Imm8(ra as u8));
                    }
                    Opcode::VSPLTB => {
                        inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::VR(VR { reg: rb as u8 }));
                        inst.operands[2] = Some(Operand::Imm8(ra as u8 & 0b1111));
                    }
                    Opcode::VSPLTH => {
                        inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::VR(VR { reg: rb as u8 }));
                        inst.operands[2] = Some(Operand::Imm8(ra as u8 & 0b111));
                    }
                    Opcode::VSPLTW => {
                        inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::VR(VR { reg: rb as u8 }));
                        inst.operands[2] = Some(Operand::Imm8(ra as u8 & 0b11));
                    }
                    Opcode::MTVSCR => {
                        inst.operands[0] = Some(Operand::VR(VR { reg: rb as u8 }));
                    }
                    Opcode::MFVSCR => {
                        inst.operands[0] = Some(Operand::VR(VR { reg: rt as u8 }));
                    }
                    other => {
                        panic!("unhandled VX-form instruction {:?}", other);
                    }
                }
            }
            Format::Z22 => {
                let rt = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let sh = (word >> 10) & 0x3f;
                let lk = word & 1;
                inst.rc = lk != 0;

                match inst.opcode {
                    Opcode::DSCLI | Opcode::DSCRI => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::Imm8(sh as u8));
                    }
                    Opcode::DSCLIQ | Opcode::DSCRIQ => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 & !1 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 & !1 }));
                        inst.operands[2] = Some(Operand::Imm8(sh as u8));
                    }
                    Opcode::DTSTDC | Opcode::DTSTDG => {
                        inst.operands[0] = Some(Operand::CrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8}));
                        inst.operands[2] = Some(Operand::Imm8(sh as u8));
                    }
                    Opcode::DTSTDCQ | Opcode::DTSTDGQ => {
                        inst.operands[0] = Some(Operand::CrField((rt >> 2) as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 & !1 }));
                        inst.operands[2] = Some(Operand::Imm8(sh as u8));
                    }
                    _other => {
                        #[cfg(test)]
                        unreachable!("new Z22-form opcode: {:?}", inst.opcode);
                    }
                }
            }
            Format::Z23 => {
                let rt = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let rb = (word >> 11) & 0x1f;
                let rmc = (word >> 9) & 0x3;
                let lk = word & 1;
                inst.rc = lk != 0;

                match inst.opcode {
                    Opcode::DQUAI => {
                        // > TE is a 5-bit signed bianry integer.
                        let te = ((ra << 3) as i8) >> 3;
                        inst.operands[0] = Some(Operand::ImmExts16(te as i16));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.operands[3] = Some(Operand::Imm8(rmc as u8));
                    }
                    Opcode::DQUAIQ => {
                        // paired registers are masked to even by objdump, we'll do similar to
                        // match..
                        inst.operands[0] = Some(Operand::Imm8(ra as u8));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rt as u8 & !1 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                        inst.operands[3] = Some(Operand::Imm8(rmc as u8));
                    }
                    Opcode::DQUA | Opcode::DRRND => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.operands[3] = Some(Operand::Imm8(rmc as u8));
                    }
                    Opcode::DQUAQ => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 & !1 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 & !1 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                        inst.operands[3] = Some(Operand::Imm8(rmc as u8));
                    }
                    Opcode::DRRNDQ => {
                        inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 & !1 }));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: ra as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                        inst.operands[3] = Some(Operand::Imm8(rmc as u8));
                    }
                    Opcode::DRINTN | Opcode::DRINTX => {
                        inst.operands[0] = Some(Operand::Imm8(ra as u8 & 1));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 }));
                        inst.operands[3] = Some(Operand::Imm8(rmc as u8));
                    }
                    Opcode::DRINTNQ | Opcode::DRINTXQ => {
                        inst.operands[0] = Some(Operand::Imm8(ra as u8 & 1));
                        inst.operands[1] = Some(Operand::FPR(FPR { reg: rt as u8 & !1 }));
                        inst.operands[2] = Some(Operand::FPR(FPR { reg: rb as u8 & !1 }));
                        inst.operands[3] = Some(Operand::Imm8(rmc as u8));
                    }
                    _other => {
                        #[cfg(test)]
                        unreachable!("new Z23-form opcode: {:?}", inst.opcode);
                    }
                }
            }
            Format::PS_LST => {
                let rt = (word >> 21) & 0x1f;
                let ra = (word >> 16) & 0x1f;
                let w = (word >> 15) & 1;
                let gqr = (word >> 12) & 0b111;
                let offset = (word & 0xfff) as i16;
                let disp = (offset << 4) >> 4;
                inst.operands[0] = Some(Operand::FPR(FPR { reg: rt as u8 }));
                inst.operands[1] = Some(Operand::MemoryDisp { base: Register { reg: ra as u8 }, disp });
                inst.operands[2] = Some(Operand::Imm8(w as u8));
                inst.operands[3] = Some(Operand::GQR(GQR { reg: gqr as u8 }));
            }
            Format::VC |
            Format::VCdot => {
                // VC and VCdot are only produced in vector instruction decoding
            }
        }
        Ok(())
    }
}