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| author | iximeow <me@iximeow.net> | 2026-04-12 01:03:47 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-05-25 00:59:27 +0000 |
| commit | a049351c5d512710f557ffb45ee6391fc86a3dc6 (patch) | |
| tree | 17040c4c95f9361de271fb1ad874c3a71d2b0e9d /CHANGELOG | |
| parent | 6c32405ca9930f393d8ca45d22df1b5a1c7c8653 (diff) | |
fix table management instructions' ({l,s}{g,i,l}dt) mem_size
these instructions, it turns out, have fixed operand size based on CPU
execution mode and regardless of prefixes. good to know!
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -10,6 +10,8 @@ * push-immediate, pushf, popf, enter, leave, and xlat now all report a correct memory access size, fixing the prior behavior of reporting no memory access size at all +* table load/store instructions (lgdt, lidt, lldt, sgdt, sidt, sldt) have correct (mode-dependent) + memory access sizes, rather than incorrectly varying on operand-size overrides. * 64-bit mode: mov seg-to-reg uses 32-bit GPRs for the destination rather than 16-bit. * this is more accurate to the semantic of the instruction, which is why other disassemblers report it this way; for register destinations specifically the segment selector is |