diff options
| author | iximeow <me@iximeow.net> | 2026-05-22 05:49:01 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-05-25 01:53:53 +0000 |
| commit | f3d52fcb08b4d1ef05583e1ca302e450e7c7b181 (patch) | |
| tree | 50bd71ac61001fdf83e54e8befa0d526ed0364c0 /CHANGELOG | |
| parent | 41e6fb71ab86cdd7007ac72ec9cb2499439037ae (diff) | |
pusha/popa/push-imm memory sizes
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 5 |
1 files changed, 2 insertions, 3 deletions
@@ -11,9 +11,8 @@ (RegSpec::xmm, RegSpec::q, RegSpec::d, RegSpec::st, etc) * for uarch-specific decoding, there is now a feature bit for Intel Key Locker. this corrects an issue where Key Locker instructions would decode under AMD-specific decoders. -* push-immediate, pushf, popf, enter, leave, and xlat now all report a correct memory - access size, fixing the prior behavior of reporting no memory access size at - all +* push-immediate, pushf, popf, pusha, popa, enter, leave, and xlat now all report a correct memory + access size, fixing the prior behavior of reporting no memory access size at all * table load/store instructions (lgdt, lidt, lldt, sgdt, sidt, sldt) have correct (mode-dependent) memory access sizes, rather than incorrectly varying on operand-size overrides. * 64-bit mode: mov seg-to-reg uses 32-bit GPRs for the destination rather than 16-bit. |