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| author | iximeow <me@iximeow.net> | 2020-05-21 23:09:39 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2020-05-21 23:09:39 -0700 |
| commit | a0fd5a24cb0aa0b697f680c451d928cefe8323b4 (patch) | |
| tree | d95069afe48249ff1226cb077e242d093bb2794a /test/protected_mode/operand.rs | |
| parent | 905dc4c7feac1e09cde70db52c0762e8990d4d96 (diff) | |
add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensions
also add builders to get decoders appropriate for specific
microarchitectures from intel and amd
* low-power architectures are not yet present
Diffstat (limited to 'test/protected_mode/operand.rs')
| -rw-r--r-- | test/protected_mode/operand.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/protected_mode/operand.rs b/test/protected_mode/operand.rs index 08a24be..8fda181 100644 --- a/test/protected_mode/operand.rs +++ b/test/protected_mode/operand.rs @@ -1,5 +1,5 @@ use yaxpeax_arch::{Decoder, LengthedInstruction}; -use yaxpeax_x86::long_mode::{DecodeError, InstDecoder, Opcode}; +use yaxpeax_x86::protected_mode::{DecodeError, InstDecoder, Opcode, Operand, RegSpec}; #[test] fn register_widths() { @@ -12,5 +12,5 @@ fn register_widths() { #[test] fn memory_widths() { - assert_eq!(Operand::RegDeref(RegSpec::rsp()).width(), 4); + assert_eq!(Operand::RegDeref(RegSpec::esp()).width(), 4); } |