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2020-11-19fix decoding of rex-prefixed modrm+sib operands selecting index 0b100 and ↵0.1.4iximeow
base 0b101 for memory operands with a base, index, and displacement either the wrong base would be selected (register number ignored, so only `*ax` or `r8*` would be reported), or yaxpeax-x86 would report a base register is present when it is not (`RegIndexBaseScaleDisp` when the operand is actually `RegScaleDisp`) thank you to Evan Johnson for catching and reporting this bug! also bump crate version to 0.1.4 as this will be immediately tagged and released.
2020-10-27Update README.md (#5)Jan
* Update README.md very typpo
2020-10-27fix misdecode of instructions in opcode 0x800.1.3iximeow
2020-08-15add RegSpec constructors, consts, and const fns0.1.2iximeow
2020-08-15forgot to strengthen that heading tooiximeow
2020-08-15add register class constants to allow reasoning about register operands0.1.1iximeow
also bump to 0.1.1
2020-08-09inaugural 0.1.0 release!0.1.0iximeow
add doc comments for public items, record changelog, and lets ship this!!
2020-08-09adjust public interface: public items should all be stableiximeow
`OperandCode` (obviously) wildly varies depending on how i feel on a given week, so it's now hidden to avoid people depending on numerical values of its discriminants. `RegisterBank` got a similar treatment with a new `RegisterClass` struct that's suitable for public use.
2020-08-09reject instructions made invalid by lock prefixesiximeow
2020-08-09support salc, get segment register numbers rightiximeow
2020-08-09tests for cltsiximeow
2020-08-09add 32-bit-only instructionsiximeow
2020-08-09port updates to protected-mode decoderiximeow
2020-08-09update protected mode testsiximeow
2020-08-09bump version0.0.15iximeow
2020-08-09unused importiximeow
2020-08-09no more incomplete decoder for vex instructionsiximeow
for now
2020-08-09support four-reg operand forms, new testsiximeow
2020-08-09add to changelogiximeow
2020-08-09avoid a bunch of checks in the likely display pathiximeow
rep_any will get speculated `false` quite quickly, whereas checking if the opcode is a string instruction will be costly no matter what. in the rare case rep_any is true, i don't care how costly displaying the instruction is - string instructions are relatively rare, and rep movs is typically not more than one instance when it shows up.
2020-08-09display opt, aykmiximeow
the arms of the match in regspec_label referenced tables that were not const. consequently, they would be rebuilt when reached, every time the match is incanted. this holds through even when regspec_label is inlined. each arm could be a const array for a small and easy change, but to avoid the indirect dispatch on spec.bank i've reorganized register names into a single const array and selected values for `RegisterBank` such that indices into that array can be formed. for my next trick, i may make `REG_NAMES` a `*const u8`, with indices picking offsets into the table - 8-byte offsets might do? this should compact down size a little more by removing a pointer and size qword for each string.
2020-08-09significantly reorganize what operands are unlikelyiximeow
likely operands are now also required to have contiguous special cases 0..31. this is to avoid generating a massively sparse jump table for no reason twice - once for unlikely_operands is quite enough as-is. this will undoubtedly be a wildly annoying maintenance burden. if this pans out (initial expiriments suggest it might) then maybe a macro will do...
2020-08-09those operands are unlikelyiximeow
2020-08-09Revert "speculative code motion"iximeow
This reverts commit 21cc850afc108c147871c70240eda62ad13f34e0.
2020-08-09speculative code motioniximeow
2020-08-09Revert "bad idea"iximeow
This reverts commit 23cbcb390c723c4c39113ce93ccff89308b6623c.
2020-08-09bad ideaiximeow
2020-08-09try to special case immediates a bitiximeow
2020-08-09centralize mem_oper assignment where possibleiximeow
2020-08-09special-case lea validity check betteriximeow
2020-08-09this makes it faster i guessiximeow
2020-08-09make address_size() no longer .. necessaryiximeow
2020-08-09more speed hole!iximeow
2020-08-09drilled a new speed hole: rex doesn't need to be held through read_M or read_sibiximeow
2020-08-09crank up the inlineriximeow
2020-08-09cmc and int1iximeow
2020-08-09invalid instruction fixiximeow
2020-08-09lea speed holeiximeow
2020-08-09speed holesiximeow
2020-08-09vinserti128iximeow
2020-08-09vextractf128iximeow
2020-08-09vpsrlqiximeow
2020-08-09vpminswiximeow
2020-08-09vpermq (avx2)iximeow
2020-08-09vpsrlw avxiximeow
2020-08-09missing avx instriximeow
2020-08-09handle bad leaiximeow
2020-08-09more popiximeow
2020-08-09long instructionsiximeow
2020-08-09loop{,z,nz}/jecxziximeow
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