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authorBrandon Ros <brandonros1@gmail.com>2026-07-03 20:48:35 -0400
committeriximeow <me@iximeow.net>2026-07-28 02:53:24 +0000
commitbbbb546ee0b73d295be891b1b2e0e5a18cbfd3d1 (patch)
tree7f20df891883d5d60a7a366d16e76b286ac91b64 /CHANGELOG
parent9e9c7b2663fa52881bf6883e74f4cd8610c38570 (diff)
fix thumb2 TBH decode: wrong opcode and register-shift operand
the T1 TBH arm set Opcode::TBB instead of Opcode::TBH, and built the index operand with bit 4 set in the RegShift raw value. bit 4 is the RegReg selector in RegShift::into_shift, so the mandatory 'lsl #1' index scaling decoded as a register shift 'lsl r0' instead. clear bit 4 so it reads back as the RegImm 'lsl #1' the encoding specifies. verified against binutils objdump: df e8 13 f0 is tbh [pc, r3, lsl #1].
Diffstat (limited to 'CHANGELOG')
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diff --git a/CHANGELOG b/CHANGELOG
index 5de5ee7..c2cc889 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -30,6 +30,7 @@ as well as thumb2 fixes from @brandonros:
* mvn (immediate) was decoded as mov,
* sxtab was decoded as sxtah,
* lsl, lsr, asr, ror were determining opcode from an incorrect bitfield,
+ * tbh was decoded as an shifted tbb,
* thumb2: (un)signed extend-and-rotate loaded an incorrect field for rotate,
thank you for the patches!