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| author | Brandon Ros <brandonros1@gmail.com> | 2026-07-03 00:14:45 -0400 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-07-28 02:53:24 +0000 |
| commit | 9e9c7b2663fa52881bf6883e74f4cd8610c38570 (patch) | |
| tree | 9646b1250f2f2bea921a582192932eda40ed3ab0 /CHANGELOG | |
| parent | eea7a08447871114c86ad3c42945847336960d2c (diff) | |
fix more thumb2 register data-processing decode bugs
- register-controlled shifts (lsl/lsr/asr/ror by register) all decoded as
lsl: the shift type was read from hw1[6:5] (always 0 for this form)
instead of hw0[6:5]
- 32-bit uxt*/sxt* extends read the ror amount from the wrong field
(hw1[2:1] scaled by 4 instead of hw1[5:4] scaled by 8), so a no-rotation
extend came back as ror #4; rotation of 0 is now omitted
- sxtab was decoded as sxtah (wrong opcode table entry)
all cases verified against binutils objdump
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -28,6 +28,9 @@ as well as thumb2 fixes from @brandonros: * thumb2: some instructions had outright incorrect opcodes: * ror (immediate) was decoded as asr, * mvn (immediate) was decoded as mov, + * sxtab was decoded as sxtah, + * lsl, lsr, asr, ror were determining opcode from an incorrect bitfield, +* thumb2: (un)signed extend-and-rotate loaded an incorrect field for rotate, thank you for the patches! |