aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2026-07-28thumb2: fix parallel addition/subtraction, (un)signediximeow
2026-07-28thumb: when nonconforming, allow it/cond=1111 like capstoneiximeow
2026-07-28thumb differential: segment out a few categories of diffiximeow
2026-07-28capstone prints thumb add/sub sp+immediate as two operandsiximeow
2026-07-28differential test should tolerate a few more differencesiximeow
2026-07-28untangle some nonconforming ld/st formsiximeow
2026-07-28lsl/mov aliasingiximeow
2026-07-28differential testing wipiximeow
2026-07-28fix thumb2 TBH decode: wrong opcode and register-shift operandBrandon Ros
2026-07-28fix more thumb2 register data-processing decode bugsBrandon Ros
2026-07-28some armv7/thumb arms are basically duplicateiximeow
2026-07-28fix several thumb2 decode bugsBrandon Ros
2026-07-28Do not add an 's' when outputing opcodes that always set flagsGrond
2026-07-28Decode the correct number of operands for TST/TEQ (immediate/register)Grond
2026-07-28Simplify decoding of register-shifted-register data-processing instructionsGrond
2026-07-28probably should decide where imm-shifted reg normalization happensiximeow
2026-07-28Decode the correct number of operands for CMP/CMN (immediate/register)Grond
2026-07-28Fix the handling of reserved bits in uncommon loads/storesGrond
2026-07-28Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2Grond
2026-07-28Implement the RRX immediate shift typeGrond
2026-07-28Fix the handling of arithmetic register shifts with zero immediatesGrond
2026-06-19Add armv7::InstDecoder::in_thumb_mode() methodSamuel Arnold
2026-02-22support A1 encoding of several coprocessor instructions + SVCrva3
2026-02-22properly display coprocessor higher than 9rva3
2026-02-22rename MCR2/MRC2 to MCR/MRCrva3
2026-02-22derive Clone and Copy for armv7 instructionrva3
2025-10-19run differential test0.4.0iximeow
2025-10-19adjust goodfile to exercise feature matrix moreiximeow
2025-10-19alloc needs yaxpeax-arch alloc tooiximeow
2025-10-19Remove empty format precision specifierMarijn Schouten
2025-10-19update changelog, no 0.3.2 after alliximeow
2025-10-19Opcode and Operand should be non-exhaustiveiximeow
2025-10-19avoid subtle changes to A64 Opcode enum discriminant choicesiximeow
2025-10-19tag instruction decode fixes, differential test precisioniximeow
2025-10-19fix opcode display for ldgMartin Fink
2025-10-19visitor-oriented fmtiximeow
2025-06-20changelog + another inlineiximeow
2025-06-02some armv7 decode helpers are trivial functions but didn't inlineiximeow
2025-05-25support the rest of PAC instructions. compare to a more recent capstoneiximeow
2025-02-060.3.10.3.1iximeow
2025-02-06actually check no-std configuration does not transitively depend on stdiximeow
2025-02-04Disable bitvec features to fix no_stdLuke Street
2024-06-25update yaxpeax-arch in differential-tests, validate in goodfileiximeow
2024-06-250.3.00.3.0iximeow
2024-06-25Bump yaxpeax-arch and bitvec, allow use of deprecated yaxpeax-arch traits, fi...novafacing
2024-06-250.2.60.2.6iximeow
2024-06-25include udf note in changelogiximeow
2024-06-25Add support for `udf`Martin Fink
2024-03-17at least armv7t doesnt panic now, but im very uncertain these are rightiximeow
2024-03-17run non-panicking tests with a horkton of parallelismiximeow
generated by cgit v1.1 at 2026-09-11 21:58:41 +0000