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2026-08-06cdp/mrc/mcr opc1 is wider than display knowsiximeow
2026-08-04write condition code *before* .w suffixiximeow
2026-08-04more leftover capstone cs_insn reuse stuffiximeow
2026-08-04msr confusion like with mrs..iximeow
2026-08-03use cs_disasm() to stop inheriting bogus cc stateiximeow
2026-08-03armv8 thumb-mode hintsiximeow
2026-08-03wip differential support (differences mostly understood)iximeow
2026-08-03decode unknown wide hints like any other hintsiximeow
2026-08-03thumb differential: much more reasonable operand parsing for memory ops..iximeow
2026-08-02fix swapped rfe{ia,db} and srs{ia,db}iximeow
2026-08-02fix missing decode of `s` bit for wide shift/rotate opsiximeow
2026-08-02thumb ldc/stc encodings missed a bitiximeow
2026-08-02sufficiently advanced SIMD is indistinguishable from coprocessorsiximeow
2026-08-02thumb2 preload improvementsiximeow
2026-08-02thumb SIMD encoding should have returned Incompleteiximeow
2026-08-02pkhbt/pkhtb bitmask confusioniximeow
2026-08-02Test Target, fix bogus MRS destinationsiximeow
2026-08-02ldrexd changelogiximeow
2026-08-02thumb mrs/msr first operand was wildly wrongiximeow
2026-07-28temp, armv8-thumbiximeow
2026-07-28thumb2: fix parallel addition/subtraction, (un)signediximeow
2026-07-28thumb: when nonconforming, allow it/cond=1111 like capstoneiximeow
2026-07-28thumb differential: segment out a few categories of diffiximeow
2026-07-28capstone prints thumb add/sub sp+immediate as two operandsiximeow
2026-07-28differential test should tolerate a few more differencesiximeow
2026-07-28untangle some nonconforming ld/st formsiximeow
2026-07-28lsl/mov aliasingiximeow
2026-07-28differential testing wipiximeow
2026-07-28fix thumb2 TBH decode: wrong opcode and register-shift operandBrandon Ros
2026-07-28fix more thumb2 register data-processing decode bugsBrandon Ros
2026-07-28some armv7/thumb arms are basically duplicateiximeow
2026-07-28fix several thumb2 decode bugsBrandon Ros
2026-07-28Do not add an 's' when outputing opcodes that always set flagsGrond
2026-07-28Decode the correct number of operands for TST/TEQ (immediate/register)Grond
2026-07-28Simplify decoding of register-shifted-register data-processing instructionsGrond
2026-07-28probably should decide where imm-shifted reg normalization happensiximeow
2026-07-28Decode the correct number of operands for CMP/CMN (immediate/register)Grond
2026-07-28Fix the handling of reserved bits in uncommon loads/storesGrond
2026-07-28Check all of the appropriate bits when parsing op1 for CDP2/MCR2/MRC2Grond
2026-07-28Implement the RRX immediate shift typeGrond
2026-07-28Fix the handling of arithmetic register shifts with zero immediatesGrond
2026-06-19Add armv7::InstDecoder::in_thumb_mode() methodSamuel Arnold
2026-02-22support A1 encoding of several coprocessor instructions + SVCrva3
2026-02-22properly display coprocessor higher than 9rva3
2026-02-22rename MCR2/MRC2 to MCR/MRCrva3
2026-02-22derive Clone and Copy for armv7 instructionrva3
2025-10-19run differential test0.4.0iximeow
2025-10-19adjust goodfile to exercise feature matrix moreiximeow
2025-10-19alloc needs yaxpeax-arch alloc tooiximeow
2025-10-19Remove empty format precision specifierMarijn Schouten
generated by cgit v1.1 at 2026-09-11 22:30:10 +0000