| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 6 hours | fix issues around unpredictable ldrd and offset printing | iximeow | |
| 6 hours | fix {s,u}xt{h,b}[16] using an immediate to describe their rotates | iximeow | |
| 6 hours | fix mrc/mrc2 use of CRd=15 | iximeow | |
| 2026-08-06 | cdp/mrc/mcr opc1 is wider than display knows | iximeow | |
| i *think* this is fixing an issue that was introduced in the diff between 0.4.0 and 0.5.0, so it's elided from the changelog.. | |||
| 2026-08-04 | write condition code *before* .w suffix | iximeow | |
| 2026-08-04 | msr confusion like with mrs.. | iximeow | |
| 2026-08-03 | armv8 thumb-mode hints | iximeow | |
| 2026-08-03 | decode unknown wide hints like any other hints | iximeow | |
| 2026-08-02 | fix swapped rfe{ia,db} and srs{ia,db} | iximeow | |
| 2026-08-02 | fix missing decode of `s` bit for wide shift/rotate ops | iximeow | |
| 2026-08-02 | thumb ldc/stc encodings missed a bit | iximeow | |
| 2026-08-02 | sufficiently advanced SIMD is indistinguishable from coprocessors | iximeow | |
| 2026-08-02 | thumb2 preload improvements | iximeow | |
| 2026-08-02 | thumb SIMD encoding should have returned Incomplete | iximeow | |
| 2026-08-02 | pkhbt/pkhtb bitmask confusion | iximeow | |
| 2026-08-02 | Test Target, fix bogus MRS destinations | iximeow | |
| 2026-08-02 | thumb mrs/msr first operand was wildly wrong | iximeow | |
| 2026-07-28 | temp, armv8-thumb | iximeow | |
| 2026-07-28 | thumb2: fix parallel addition/subtraction, (un)signed | iximeow | |
| 2026-07-28 | thumb: when nonconforming, allow it/cond=1111 like capstone | iximeow | |
| 2026-07-28 | lsl/mov aliasing | iximeow | |
| 2026-07-28 | differential testing wip | iximeow | |
| 2026-07-28 | fix thumb2 TBH decode: wrong opcode and register-shift operand | Brandon Ros | |
| the T1 TBH arm set Opcode::TBB instead of Opcode::TBH, and built the index operand with bit 4 set in the RegShift raw value. bit 4 is the RegReg selector in RegShift::into_shift, so the mandatory 'lsl #1' index scaling decoded as a register shift 'lsl r0' instead. clear bit 4 so it reads back as the RegImm 'lsl #1' the encoding specifies. verified against binutils objdump: df e8 13 f0 is tbh [pc, r3, lsl #1]. | |||
| 2026-07-28 | fix more thumb2 register data-processing decode bugs | Brandon Ros | |
| - register-controlled shifts (lsl/lsr/asr/ror by register) all decoded as lsl: the shift type was read from hw1[6:5] (always 0 for this form) instead of hw0[6:5] - 32-bit uxt*/sxt* extends read the ror amount from the wrong field (hw1[2:1] scaled by 4 instead of hw1[5:4] scaled by 8), so a no-rotation extend came back as ror #4; rotation of 0 is now omitted - sxtab was decoded as sxtah (wrong opcode table entry) all cases verified against binutils objdump | |||
| 2026-07-28 | some armv7/thumb arms are basically duplicate | iximeow | |
| 2026-07-28 | fix several thumb2 decode bugs | Brandon Ros | |
| - 32-bit store encodings with the imm12 bit (bit 23) set were decoded as the register-offset form when imm12 < 64, or as strbt/strht/strt when imm12 was 0xExx. bit 23 set always means the imm12 form. - movw/movt packed imm4 at bit 16 instead of bit 12, producing 20-bit immediates (e.g. 0xf0005 instead of 0xf005) - mvn (immediate) was decoded as mov, dropping the bitwise not - ror (immediate) was decoded as asr all cases verified against binutils objdump | |||
| 2026-07-28 | Do not add an 's' when outputing opcodes that always set flags | Grond | |
| 2026-07-28 | Implement the RRX immediate shift type | Grond | |
| 2026-02-22 | support A1 encoding of several coprocessor instructions + SVC | rva3 | |
| initially was "implement MCR/MRC decoding", but expanded to include the whole coprocessor space for completeness, and then SVC is right there too. Neon instructions in this space are still rejected, as neon support is not really there yet. Co-authored-by: iximeow <me@iximeow.net> | |||
| 2026-02-22 | properly display coprocessor higher than 9 | rva3 | |
| 2026-02-22 | rename MCR2/MRC2 to MCR/MRC | rva3 | |
| they share exactly the same encoding, except the high bits for condition the bool indicates if it's A2 encondings which is unconditional | |||
| 2025-10-19 | visitor-oriented fmt | iximeow | |
| this makes a decode+format benchmark drop from 75s to 14s... (decode is 5s) | |||
| 2024-06-25 | Bump yaxpeax-arch and bitvec, allow use of deprecated yaxpeax-arch traits, ↵ | novafacing | |
| fix bitvec syntax changes | |||
| 2024-03-17 | at least armv7t doesnt panic now, but im very uncertain these are right | iximeow | |
| 2022-09-29 | Fix 32-bit conditional thumb branches | Mitchell Johnson | |
| Correct the shift used to select condition bits and correctly compute the branch offset. | |||
| 2022-09-29 | Fix negative unconditional 16-bit thumb branches | Mitchell Johnson | |
| Sign extension shift had an off-by-one error so the sign bit was not being properly extended. | |||
| 2022-09-29 | Fix 32-bit Thumb unconditional branch decoding | Mitchell Johnson | |
| T4 encodings of unconditional branches were not being interpreted correctly (#6), and 32-bit bl/blx instructions were similarly incorrect. Correct the bits selected for op1 and op2 and handle the slightly-unusual i1/i2 sign bit xor for these instructions. | |||
| 2022-01-02 | fix docs that failed to build | iximeow | |
| 2021-09-28 | fix various armv8 and armv8 panics that should be Err. | iximeow | |
| in fact the decoder should _never_ panic. included here are tests that cover the entire 32-bit instruction space and ensure that decoding and display do not panic. these tests run uncomfortably slowly (1168s to decode the 4b "instruction" sequences on my desktop), but verify that panics are no longer an issue. | |||
| 2021-07-06 | update yaxpeax_arch and bump version to 0.1.00.1.0 | iximeow | |
| 2020-12-06 | TODONE: adr with add/subtracted offset | iximeow | |
| instead of trying to shoehorn in `adr reg, label` syntax like the manual requests, it's much easier to just describe these as `{add, sub} reg, pc, offset` and potentially rewrite `pc, offset` as an `adr reg, label` if a higher-level tool has that kind of information available. | |||
| 2020-12-06 | propagate up invalid thumb immediate expansion | iximeow | |
| 2020-12-06 | warning cleanup (test edition) | iximeow | |
| add in some simd tests for future neon decoding. these tests are drawn from capstone and may need some subsequent cleanup | |||
| 2020-12-06 | support CPS (change processor state) and some warming cleanup | iximeow | |
| 2020-12-06 | add ldc/sdc instructions and a slew of 32b thumb2 tests | iximeow | |
| 2020-12-06 | support more mul/div variants | iximeow | |
| 2020-12-06 | thumb parallel addition and subtraction | iximeow | |
| 2020-12-06 | fill out more missing thumb2 decoder | iximeow | |
| 2020-12-06 | fix more incomplete cases, report arm instruction length properly | iximeow | |
| 2020-12-06 | remove "Incomplete" opcode from arm7 non-thumb decoder | iximeow | |
 |
index : yaxpeax-arm | |
| yaxpeax arm decoder |
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