aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
5 hoursadapt long-mode behavior support to protected mode and real modeiximeow
7 hoursadd behavior information for x86_64 instructionsiximeow
9 hours66-prefixed sha1rnds4 doesnt even realiximeow
9 hoursgpr register size in real/protected modeiximeow
10 hoursdisallow 66-prefixed sha1rnds4iximeow
10 hourspusha/popa/push-imm memory sizesiximeow
10 hourshelpers to create cr0-cr7iximeow
10 hoursworking through a bunch of avx512 stuff, regspec constructors are constiximeow
10 hourspextr*/extractpsiximeow
10 hoursfeature guard for key lockeriximeow
10 hoursinvept precisioniximeow
10 hoursmore precision for vinsert/vextract/vblendv{ps,pd}iximeow
10 hoursactually support avx/f16c in per-uarch decodingiximeow
10 hoursvmaskmovdqu, vmovq were also incorrect in some ways...iximeow
11 hoursmore general avx improvementsiximeow
11 hourscleanup pass on vex-encoded instructions is going to be excitingiximeow
11 hoursreport memory access size for "monitor"iximeow
11 hoursmaskmov{q,dqu} memory access sizeiximeow
11 hoursmore precise about 0f0d prefetch/nopiximeow
11 hoursfix table management instructions' ({l,s}{g,i,l}dt) mem_sizeiximeow
11 hoursmore accurate mov seg-to-gpr operand sizeiximeow
11 hourspush/pop for segment registers has implicit memory accessiximeow
11 hourspushf, popf, enter, leave, xlat all have implicit memory accessiximeow
11 hoursadd initial stats for disasm stats in all modesiximeow
11 hoursgoodfile should use shas directly for local untagged refsiximeow
2026-02-22correct push-immediate memory access sizeiximeow
2026-02-14fair enough on those warningsiximeow
2026-02-14type aliases make some of these signatures less egregious..iximeow
2026-02-14uarch settings for apx, avx10.1, etc + nouns get capsiximeow
2025-09-29fix broken capstone_bench stuff, might delete later, idkiximeow
2025-09-29annotation description test requires `fmt`iximeow
2025-06-02changelog should note ISA extension changesiximeow
2025-06-013dnow was still supported on K8, K10. 32-bit mode should learn about uarch tw...iximeow
2025-06-01describe the per-isa extensions a bit betteriximeow
2025-06-01revise_instruction is the same on all bitnesses, so macro it tooiximeow
2025-06-01DecodeEverything wasn't useful, no better than InstDecoder::default()??iximeow
2025-06-01cpu feature bits are the same across 64/32/16-bitiximeow
2025-06-01expand isa feature selection to more bitsiximeow
2024-06-24summary description of opt work2.0.0iximeow
2024-06-24document one more stray unsafeiximeow
2024-06-24add missing feature flag to real-mode ffi libraryiximeow
2024-06-24bench: fetch from fork updated for yaxpeax-x86 2.0.0iximeow
2024-06-24bump cargo version to 2.0.0, not quite releasing yetiximeow
2024-06-24justify the current max instruction lengthiximeow
2024-06-24consistently enter register/number/opcode spansiximeow
2024-06-24one more stray docs erroriximeow
2024-06-24rename most operand variants, make them structy rather than tupleyiximeow
2024-06-23remove selects_cs(), cs() now does the right thingiximeow
2024-06-23note yaxpeax-arch version bump in changelogiximeow
2024-06-23update yaxpeax-arch to 0.3.1, fix fuzz target warningsiximeow