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| author | iximeow <me@iximeow.net> | 2026-08-02 23:43:23 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-08-02 23:43:23 +0000 |
| commit | 4281309f580130c3642d50b79034f0428b662c55 (patch) | |
| tree | 6375b8dbe6f628afedc4605f83d0d9f78949e70a /CHANGELOG | |
| parent | b89b56f1e92b9559ccd11929e575db3ea2b71ced (diff) | |
fix swapped rfe{ia,db} and srs{ia,db}
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -16,6 +16,7 @@ saved) program status register, was reported as a banked GPR. * thumb2: some coprocessor instructions were incorrectly decoded as `ldc*/stc*` * thumb2: fix missing decode of `s` bit for wide lsl/lsr/asr/ror (register) +* thumb2: rfeia and rfedb were decoded backwards. likewise for srsia and srsdb * ARMv8: support thumb2 encoding of `Test Target` instruction, `Opcode::TT` (formatted as any of `tt`, `ttt`, `tta`, `ttat`) * ARMv8: formerly-coprocessor instructions have been defined into SIMD extensions, |
