| Age | Commit message (Expand) | Author |
|---|
| 2026-08-04 | msr confusion like with mrs.. | iximeow |
| 2026-08-03 | armv8 thumb-mode hints | iximeow |
| 2026-08-03 | decode unknown wide hints like any other hints | iximeow |
| 2026-08-02 | fix swapped rfe{ia,db} and srs{ia,db} | iximeow |
| 2026-08-02 | fix missing decode of `s` bit for wide shift/rotate ops | iximeow |
| 2026-08-02 | thumb ldc/stc encodings missed a bit | iximeow |
| 2026-08-02 | sufficiently advanced SIMD is indistinguishable from coprocessors | iximeow |
| 2026-08-02 | thumb2 preload improvements | iximeow |
| 2026-08-02 | thumb SIMD encoding should have returned Incomplete | iximeow |
| 2026-08-02 | pkhbt/pkhtb bitmask confusion | iximeow |
| 2026-08-02 | Test Target, fix bogus MRS destinations | iximeow |
| 2026-08-02 | thumb mrs/msr first operand was wildly wrong | iximeow |
| 2026-07-28 | temp, armv8-thumb | iximeow |
| 2026-07-28 | thumb2: fix parallel addition/subtraction, (un)signed | iximeow |
| 2026-07-28 | thumb: when nonconforming, allow it/cond=1111 like capstone | iximeow |
| 2026-07-28 | lsl/mov aliasing | iximeow |
| 2026-07-28 | differential testing wip | iximeow |
| 2026-07-28 | fix thumb2 TBH decode: wrong opcode and register-shift operand | Brandon Ros |
| 2026-07-28 | fix more thumb2 register data-processing decode bugs | Brandon Ros |
| 2026-07-28 | some armv7/thumb arms are basically duplicate | iximeow |
| 2026-07-28 | fix several thumb2 decode bugs | Brandon Ros |
| 2026-07-28 | Do not add an 's' when outputing opcodes that always set flags | Grond |
| 2026-07-28 | Implement the RRX immediate shift type | Grond |
| 2026-02-22 | support A1 encoding of several coprocessor instructions + SVC | rva3 |
| 2026-02-22 | properly display coprocessor higher than 9 | rva3 |
| 2026-02-22 | rename MCR2/MRC2 to MCR/MRC | rva3 |
| 2025-10-19 | visitor-oriented fmt | iximeow |
| 2024-06-25 | Bump yaxpeax-arch and bitvec, allow use of deprecated yaxpeax-arch traits, fi... | novafacing |
| 2024-03-17 | at least armv7t doesnt panic now, but im very uncertain these are right | iximeow |
| 2022-09-29 | Fix 32-bit conditional thumb branches | Mitchell Johnson |
| 2022-09-29 | Fix negative unconditional 16-bit thumb branches | Mitchell Johnson |
| 2022-09-29 | Fix 32-bit Thumb unconditional branch decoding | Mitchell Johnson |
| 2022-01-02 | fix docs that failed to build | iximeow |
| 2021-09-28 | fix various armv8 and armv8 panics that should be Err. | iximeow |
| 2021-07-06 | update yaxpeax_arch and bump version to 0.1.00.1.0 | iximeow |
| 2020-12-06 | TODONE: adr with add/subtracted offset | iximeow |
| 2020-12-06 | propagate up invalid thumb immediate expansion | iximeow |
| 2020-12-06 | warning cleanup (test edition) | iximeow |
| 2020-12-06 | support CPS (change processor state) and some warming cleanup | iximeow |
| 2020-12-06 | add ldc/sdc instructions and a slew of 32b thumb2 tests | iximeow |
| 2020-12-06 | support more mul/div variants | iximeow |
| 2020-12-06 | thumb parallel addition and subtraction | iximeow |
| 2020-12-06 | fill out more missing thumb2 decoder | iximeow |
| 2020-12-06 | fix more incomplete cases, report arm instruction length properly | iximeow |
| 2020-12-06 | remove "Incomplete" opcode from arm7 non-thumb decoder | iximeow |
| 2020-12-06 | fix selection from wrong instr word, clean up .w suffixes | iximeow |
| 2020-12-06 | fix regimm masks | iximeow |
| 2020-12-06 | numerous one-off mis-specializations, most of ld/prefetch hints | iximeow |
| 2020-12-06 | fix off by one in a mask for data-processing (shifted register) | iximeow |
| 2020-12-06 | fix incorrect operand selection | iximeow |
