| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 21 hours | shove all the masm input/output patching into the masm tools bits.. | iximeow | |
| 22 hours | add DisplayRules, docs, doc tests, .. | iximeow | |
| this includes `trait DisplayRules` as a generic mechanism to control parts of instruction printing, a `DefaultRules` for the existing formatting style, and `AbsoluteAddressFormatter` to print instructions as at some location in an address space. | |||
| 22 hours | ucomiss/comiss vex dumpbin bug | iximeow | |
| 22 hours | fix some forms of lss/lfs/lgs having incorrectly-small memory sizes | iximeow | |
| 22 hours | protected/real mode lfs/lgs/lss | iximeow | |
| 22 hours | pextr*/pinsr*/insertps/extrps immediate is now u8 instead of i8 | iximeow | |
| 22 hours | fix seam, user-ipi, {rd,wr}{fs,gs}base instructions decoding outside 64b mode | iximeow | |
| 22 hours | set up dumpbin/masm for properly assmbling and parsing in 16/32-bit modes | iximeow | |
| 22 hours | fix vgatherdpd using incorrect simd vector width for gather indices | iximeow | |
| 22 hours | fix vpbroadcast* memory size and source register bank | iximeow | |
| 22 hours | add MASM-style formatting support in all modes | iximeow | |
| this includes a mildly nightmarish bit of test harness to compare against ml.exe/ml64.exe/dumpbin.exe, which in turn chased out a bunch of bugs. yay! | |||
| 2026-06-21 | the weird 64b movq thing was a capstone bug all along?! | iximeow | |
| 2026-06-21 | 64-bit: vex-prefix register extension.. | iximeow | |
| 2026-06-21 | fix several instructions' incorrect memory or op2 size | iximeow | |
| 2026-06-21 | rename rne-sae to rn-sae | iximeow | |
| 2026-06-21 | fix mnemonics for prefetcht* | iximeow | |
| 2026-06-21 | reworking how tests work: more modular now | iximeow | |
| this hopefully gets testcases closer to a point where one could simply write a program that dumps test bytes and expected disassembly. more immediately, this is a structure to dangle an optioanl masm-style disassembly of an instruction for testing that imminent addition too. | |||
| 2026-06-21 | feature gate kvm tests to linux | iximeow | |
| 2026-06-21 | useless use of unsafe | iximeow | |
| 2026-06-21 | Make invalid instruction constructors actually return invalid instructions | Samuel Arnold | |
| As opposed to nops. | |||
| 2026-05-26 | 2.1.12.1.1 | iximeow | |
| 2026-05-26 | fix jrcxz/jecxz/jcxz having "two operands" | iximeow | |
| 2026-05-25 | 2.1.0 is real! | iximeow | |
| 2026-05-25 | push/pop width in 16/32-bit modes are receptive to operand width prefix | iximeow | |
| 2026-05-25 | dont clobber test VM control state in tests.. | iximeow | |
| 2026-05-25 | reject arpl in 16-bit decoding | iximeow | |
| 2026-05-25 | reword changelog | iximeow | |
| 2026-05-25 | and some prefix helpers should be pub | iximeow | |
| 2026-05-25 | j*cxz/pusha/popa alternate size forms | iximeow | |
| these all existed since forever but the library did not distinguish them and did not provide prefix information for users to tell which had been decoded. | |||
| 2026-05-25 | enable internal asserts during fuzzing | iximeow | |
| 2026-05-25 | adapt long-mode behavior support to protected mode and real mode | iximeow | |
| along the way, fix an error: maskmov is memory read-write. additionally, operand information about {push,pop}a{,d}. | |||
| 2026-05-25 | add behavior information for x86_64 instructions | iximeow | |
| this is a squash of a few months' hacking, including but not limited to what eventually got extracted into https://git.iximeow.net/asmlinator/about/ the path here is generally not historically interesting, and the vast majority of this diff is very particular static data tables (BehaviorDigests and implicit operand lists) `src/long_mode/behavior.rs` will more or less be directly adapted into versions for x86-32 and x86-16, similar to the instruction decoders. | |||
| 2026-05-25 | 66-prefixed sha1rnds4 doesnt even real | iximeow | |
| 2026-05-25 | gpr register size in real/protected mode | iximeow | |
| 2026-05-25 | disallow 66-prefixed sha1rnds4 | iximeow | |
| 2026-05-25 | pusha/popa/push-imm memory sizes | iximeow | |
| 2026-05-25 | helpers to create cr0-cr7 | iximeow | |
| 2026-05-25 | working through a bunch of avx512 stuff, regspec constructors are const | iximeow | |
| 2026-05-25 | pextr*/extractps | iximeow | |
| 2026-05-25 | feature guard for key locker | iximeow | |
| 2026-05-25 | invept precision | iximeow | |
| 2026-05-25 | more precision for vinsert/vextract/vblendv{ps,pd} | iximeow | |
| 2026-05-25 | actually support avx/f16c in per-uarch decoding | iximeow | |
| 2026-05-25 | vmaskmovdqu, vmovq were also incorrect in some ways... | iximeow | |
| 2026-05-25 | more general avx improvements | iximeow | |
| 2026-05-25 | cleanup pass on vex-encoded instructions is going to be exciting | iximeow | |
| 2026-05-25 | report memory access size for "monitor" | iximeow | |
| 2026-05-25 | maskmov{q,dqu} memory access size | iximeow | |
| 2026-05-25 | more precise about 0f0d prefetch/nop | iximeow | |
| 2026-05-25 | fix table management instructions' ({l,s}{g,i,l}dt) mem_size | iximeow | |
| these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know! | |||
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